IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 351
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter :
Descriptor/Data Interface
Table C–15. Performance and Resource Utilization, Descriptor/Data Interface - Stratix IV Family
December 2010 Altera Corporation
×1/ ×4
×1
×1
×4
×4
Stratix IV Family
Table C–15
Stratix IV (EP4SGX290FH29C2X) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 10.1.
Clock (MHz)
Parameters
Internal
125
125
125
125
shows the typical expected performance and resource utilization of
Channels
Virtual
1
2
1
2
Combinational
ALUTs
5200
6200
6800
7900
Dedicated
Registers
3600
4400
4600
5500
Size
PCI Express Compiler User Guide
M9K Memory
Blocks
10
5
8
7
C–9
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