IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 11

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function Suite
Features
Features
General Description
January 2011 Altera Corporation
Table 1–3. Device Family Support (Part 2 of 2)
The following features are common to all of the Video and Image Processing Suite
MegaCore functions:
■
■
■
■
■
■
This section provides a general description of each MegaCore function in the Video
and Image Processing Suite.
Cyclone III
Cyclone III LS
Cyclone IV GX
HardCopy II
HardCopy III
HardCopy IV
Stratix
Stratix II
Stratix III
Stratix IV
Stratix V
Other device families
Common Avalon
Avalon Memory-Mapped (Avalon-MM) interfaces for run-time control input and
connections to external memory blocks
Easy-to-use parameter editor for parameterization and hardware generation
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore Plus evaluation
SOPC Builder ready
1
®
SOPC Builder systems use an active low reset while the Video and Image
Processing Suite MegaCore functions use an active high reset. Arbitrator
logic in SOPC Builder automatically inverts the reset signals.
Device Family
®
Streaming (Avalon-ST) interface and Avalon-ST Video protocol
Final
Preliminary
Preliminary
HardCopy Compilation
HardCopy Companion
HardCopy Companion
Final
Final
Final
Final
Preliminary
No support
Video and Image Processing Suite User Guide
Support
1–3