IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 116

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Control Synchronizer
Video and Image Processing Suite User Guide
Using the Control Synchronizer
You can use the Control Synchronizer MegaCore function to synchronize the
configuration of other MegaCore functions with an event in the video stream. The
control synchronizer has an Avalon Video Streaming Input and Output port, which
passes through Avalon-ST Video data, and monitors the data for trigger events. The
events that can trigger the control synchronizer are the start of a video data packet, or
a change in the width or height field of a control data packet that describes the next
video data packet.
The Control Synchronizer MegaCore function also has an Avalon Master port. When
the Control Synchronizer MegaCore function detects a trigger event the MegaCore
writes data to the Avalon Slave control ports of other MegaCores. The Control
Synchronizer MegaCore function also has an Avalon Slave port that sets the data to be
written and the addresses that the data should be written to when the MegaCore
function detects a trigger event.
When the Control Synchronizer MegaCore function detects a trigger event, it
immediately stalls the Avalon-ST video data flowing through the MegaCore, which
freezes the state of other MegaCore functions on the same video processing data path
that do not have buffering in between. The Control Synchronizer then writes the data
stored in its Avalon Slave register map to the addresses that are also specified in the
register map. Once this writing is complete the Control Synchronizer resumes the
Avalon-ST video data flowing through it. This function ensures that any cores after
the Control Synchronizer have their control data updated before the start of the video
data packet to which the control data applies. Once all the writes from a Control
Synchronizer trigger are complete, an interrupt is triggered or is initiated, which is the
“completion of writes” interrupt.
The control synchronizer has an address in its Avalon Slave Control port that you can
use to disable or enable the trigger condition. The Control Synchronizer can
optionally be configured before compilation to set this register to the “disabled” value
after every trigger event, this is useful when using the control synchronizer to trigger
only on a single event.
This section provides an example of how to use the Control Synchronizer MegaCore
function. The Control Synchronizer is set to trigger on the changing of the width field
of control data packets. In the following example, the Control Synchronizer is placed
in a system containing a Test Pattern Generator, a Frame Buffer, and a Scaler. The
Control Synchronizer must synchronize a change of the width of the generated video
packets with a change to the Scaler output size, such that the Scaler maintains a
scaling ratio of 1:1 (no scaling). The Frame Buffer is configured to drop and repeat;
this makes it impossible to calculate when packets streamed into the Frame Buffer are
streamed out to the Scaler, which means that the Scaler cannot be configured in
advance of a certain video data packet. The Control Synchronizer solves this problem,
as described in the following scenario.
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Control Synchronizer