PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 78

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
11. 8-bit parallel interface
PN512
Product data sheet
COMPANY PUBLIC
10.4.12 PN512 at lower speed modes
10.4.11 Switching between F/S mode and HS mode
11.1 Overview of supported host controller interfaces
After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected PN512
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
It is possible for system configurations that do not have other I
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I
must be avoided because of the reduced spike suppression.
PN512 is fully downward-compatible and can be connected to an F/S mode I
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola
compatible modes.
The PN512 supports direct interfacing to various μ-Controllers. The following table shows
the parallel interface types supported by the PN512.
Table 151. Supported interface types
Supported interface types
Separated Read and Write
Strobes (INTEL compatible)
Multiplexed Read and Write
Strobe (Motorola compatible)
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
2. Adapt the slope control of the SDA output stages.
in HS mode.
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
2
CForceHS bit to logic 1. In permanent HS mode, the master code
Bus
control
address
data
control
address
data
111336
Separated Address and
Data Bus
NRD, NWR, NCS
A0 … A3 [..A5*]
D0 … D7
R/NW, NDS, NCS
A0 … A3 [..A5*]
D0 … D7
2
C-bus devices involved in
Multiplexed Address
and Data Bus
NRD, NWR, NCS, ALE
AD0 … AD7
AD0 … AD7
R/NW, NDS, NCS, AS
AD0 … AD7
AD0 … AD7
Transmission module
© NXP B.V. 2011. All rights reserved.
PN512
2
2
C-bus lines
C-bus
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