PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 89

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
12.7.3 Additional hardware support for FeliCa and NFC
12.7.4 CRC coprocessor
Additionally to the polling sequence support for the Felica mode, the PN512 supports the
check of the Len-byte.
The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg:
DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet
length. This register is six bit long. Each bit represents a length of four bytes.
DataLenMax in register FelNFC2Reg defines the maximum length of the accepted
package. This register is six bit long. Each bit represents a length of four bytes. If set to
logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not
transferred to the FIFO and receiving is kept active.
Example 1:
Example 2:
The following CRC coprocessor parameters can be configured:
Table 155. CRC coprocessor parameters
Parameter
CRC register length
CRC algorithm
CRC preset value
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•
•
•
•
•
•
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DataLenMin = 4
– The length shall be greater or equal 16.
DataLenMax = 5
– The length shall be smaller than 20. Valid area: 16, 17, 18, 19
DataLenMin = 9
– The length shall be greater or equal 36.
DataLenMax = 0
– The length shall be smaller than 256. Valid area: 36 to 255
The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
The CRC polynomial for the 16-bit CRC is fixed to x
The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB
first.
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
Value
16-bit CRC
algorithm according to ISO/IEC 14443 A and ITU-T
0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bits
111336
16
+ x
12
+ x
Transmission module
5
+ 1
© NXP B.V. 2011. All rights reserved.
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