UBA2014TD-T NXP Semiconductors, UBA2014TD-T Datasheet - Page 5

• Manufacturer Part Number: UBA2014TD-T
• Description: Display Drivers TL BALLAST
• Manufacturer: NXP Semiconductors

Specifications of UBA2014TD-T

• Driver Type: CCFL, HFTL Drivers
• Maximum Operating Temperature: + 80 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: UBA2014T/N1,518

NXP Semiconductors
8. Functional description
UBA2014_4
Product data sheet
8.1 Start-up state
8.2 Oscillation
8.3 Adaptive non-overlap
8.4 Timing circuit
Initial start-up can be achieved by charging the low-voltage supply capacitor C7
(see
condition that both half bridge transistors TR1 and TR2 are non-conductive. The circuit
will be reset in the start-up state. If the low-voltage supply (V
V
(HS) driver. Below the lockout voltage at the FV
zero. The voltages at pins CF and CT are zero during the start-up state.
The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the V
determined by capacitor C
and maximum switching frequencies are determined by R
internally fixed. The sawtooth frequency is twice the half bridge frequency. The UBA2014
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is illustrated in
Figure
Low-Side (LS) transistor is switched on. The first conducting time is made extra long to
enable the bootstrap capacitor to charge.
The non-overlap time is realized with an Adaptive Non-overlap circuiT (ANT). By using an
adaptive non-overlap circuit, the application can determine the duration of the non-overlap
time and make it optimum for each frequency; see
determined by the slope of the half bridge voltage, and is detected by the signal across
resistor R16 which is connected directly to pin ACM. The minimum non-overlap time is
internally fixed. The maximum non-overlap time is internally fixed at approximately 25 %
of the bridge period time. An internal filter of 30 ns is included at the ACM pin to increase
the noise immunity.
A timing circuit is included to determine the preheat time and the ignition time. The circuit
consists of a clock generator and a counter.
The preheat time is defined by C
maximum ignition time is 1 pulse at C
start-up state, as soon as the low supply voltage (V
critical value of the lamp voltage (V
C
DD(start)
CT
is discharged to 0 V at 1 mA.
Figure
4. The oscillator starts oscillating at f
the circuit will start oscillating. A DC reset circuit is incorporated in the High-Side
8) via an external start-up resistor. Start-up of the circuit is achieved under the
Rev. 04 — 16 October 2008
CF
, resistor R
CT
CF(high)
lamp(fail)
and R
CT
IREF
. The timing circuit starts operating after the
level and 0 V. The frequency of the sawtooth is
IREF
) is exceeded. When the timer is not operating
, and the voltage at pin CSW. The minimum
max
and consists of 7 pulses at C
600 V driver IV for HF fluorescent lamps
. During the first switching cycle the
DD
pin the output voltage (V
Figure
DD
) has reached V
IREF
4. The non-overlap time is
DD
and C
) reaches the value of
CF
DD(start)
UBA2014
; their ratio is
© NXP B.V. 2008. All rights reserved.
GH
CT
or when a
; the
V
SH
5 of 19
) is