HV9982 Supertex, HV9982 Datasheet - Page 9

• Manufacturer Part Number: HV9982
• Description: LED Drivers 3-Channel LED High Accuracy
• Manufacturer: Supertex

Thus, the maximum time required to discharge the inductors
can be computed as:
The hiccup time is then chosen as:
False Triggering of the Short Circuit Compara-
tor During PWM Dimming
During PWM dimming, the parasitic capacitance of the LED
string causes a spike in the output current when the discon-
nect FET is turned on. If this spike is detected by the short
circuit comparator, it will cause the IC to falsely detect an
over current condition and shut down.
In the HV9982, to prevent these false triggerings, there is
a built in 500ns blanking network for the short circuit com-
parator. This blanking network is activated when the PWMD
input goes high. Thus, the short circuit comparator will not
see the spike in the LED current during the PWM Dimming
turn-on transition. Once the blanking timer is completed, the
short circuit comparator will start monitoring the output cur-
rent. Thus, the total delay time for detecting a short circuit
will depend on the condition of the PWMD input.
If the output short circuit exists before the PWM dimming
signal goes high, the total detection time will be:
If the short circuit occurs when the PWM dimming signal is
already high, the time to detect will be:
Over Voltage Protection
The HV9982 provides hysteretic over voltage protection al-
lowing the IC to recover in case the LED load is momentarily
disconnected.
When the load is disconnected in a boost converter, the
output voltage rises as the output capacitor starts charging.
When the output voltage reaches the OVP rising threshold,
the HV9982 detects an over voltage condition and turns off
the converter. The converter is turned back on only when the
output voltage falls below the falling OVP threshold (which
is 10% lower than the rising threshold). This time is mostly
dictated by the R-C time constant of the output capacitor C
and the resistor network used to sense over voltage (R
R
cle keeps repeating maintaining the output voltage within a
10% band.
OVP2
). In case of a persistent open circuit condition, this cy-
t
t
t
t
ind,max
hiccup
detect1
detect1
Supertex inc.
> max (t
= t
= t
= max (t
BLANK
DELAY
+ t
≈ 250ns(max)
COMP,max
ind1
DELAY
, t
ind2
, t
≈ 950ns(max)
, t
ind,max
ind3
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1235 Bordeaux Drive, Sunnyvale, CA 94089
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OVP1
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9
In most designs, the lower threshold voltage of the over volt-
age protection (V
tempts to restart will be more than the LED string voltage.
Thus, when the LED load is reconnected to the output of the
converter, the voltage differential between the actual output
voltage and the LED string voltage will cause a spike in the
output current. This causes a short circuit to be detected and
the HV9982 will trigger short circuit protection. This behavior
continues till the output voltage becomes lower than the LED
string voltage at which point, no fault will be detected and
normal operation of the circuit will commence.
Layout Considerations
For multi-channel peak current mode controller IC to work
properly with minimum interference between the channels,
it is important to have a good PCB layout which minimizes
noise. Following the layout rules stated below will help to
ensure proper performance of all three channels.
1. GND connection
2. VDD Connection
3. REF Connection
4. GATE and CS connection
5. OVP protection
The IC has four separate ground connections – one
for each of the three channels and one analog ground
for the common circuitry. It is recommended that four
separate ground planes be used in the PCB and all the
GND planes be connected together at the return termi-
nal of the input power lines.
Each VDD pin should be by passed with a low ESR
capacitor to its OWN ground (i.e. VDD1 is bypassed
to GND1 and so on). The common VDD pin can be
bypassed to the common GND.
In case all the references are going to be driven from
a single voltage source, it is recommended to have a
small R-C low pass filter (1.0k, 1.0nF) at each REF
pin with the filter being referenced to the appropriate
channel’s ground (as in the case of the VDD pins). If
the REF pins are driven with three individual voltage
sources, then just a small capacitor (1.0nF) at each pin
would suffice.
The connection from GATE output to the gate of the ex-
ternal FET as well as the connection from the CS pin to
the external sense resistor made as short as possible
to avoid false triggering.
Typically, the OVP resistor dividers would be located
away from the IC. To prevent false triggering of the IC
due to noise at the OVP pin, a small bypass capacitor
(1.0nF) right at the OVP pin is recommended.
●
Tel: [phone]
OVP
– 10%) at which point the HV9982 at-
●
www.supertex.com
HV9982