ZHX2022MV040THTR Zilog, ZHX2022MV040THTR Datasheet - Page 19

• Manufacturer Part Number: ZHX2022MV040THTR
• Description: Fiber Optic Transmitters, Receivers, Transceivers FIR IrDA 4 MBITS
• Manufacturer: Zilog

Specifications of ZHX2022MV040THTR

• Product: Transceiver
• Data Rate: 115.2 Kbps
• Wavelength: 900 nm
• Maximum Rise Time: 40 ns
• Maximum Fall Time: 40 ns
• Pulse Width Distortion: 1.8 us
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Package / Case: UltraSlim
• Idle Current, Typ @ 25° C: 2mA
• Link Range, Low Power: -
• Operating Temperature: -25°C ~ 85°C
• Orientation: Top View
• Shutdown: *
• Size: 9.7mm x 4.7mm x 4mm
• Standards: IrPHY 1.4
• Supply Voltage: 2.7 V ~ 5.5 V
• Lead Free Status: Contains lead
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Recommended SMD Pad Layout
PS021802-1005
Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s)
Note:
4. After waiting t
After that, Txd is enabled as normal Txd input, and the transceiver is set for the
high bandwidth (576 kbit/s to 4 Mbit/s) mode.
1. Set SD input to logic “HIGH”.
2. Set Txd input to logic “LOW”. Wait t
3. Set SD to logic “LOW” (this negative edge latches state of Txd, which
4. Txd must be held for t
After that Txd is enabled as normal Txd input and the transceiver is set for the
lower bandwidth (9.6 kbit/s to 115.2 kbit/s) mode.
The leads of the device should be soldered in the center position of the pads. For
more configurations, see inside the device drawing.
Figure 5. Pad Layout (mm)
is limited by the maximum allowed pulse length.
determines speed setting).
Leads of the device should be at least 0.3 mm within the ends of the pads.
h
> 200 ns, Txd can be set to logic “LOW”. The hold time of Txd
h
> 200 ns.
s
> 200 ns.
FIR Transceiver
15