71M6521FEIM-DB Maxim Integrated Products, 71M6521FEIM-DB Datasheet - Page 104

• Manufacturer Part Number: 71M6521FEIM-DB
• Description: Power Management Modules & Development Tools 71M6521FE DEMO BOARD M6521FE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FEIM-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the
external data RAM.
In the first type (MOVX@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits
of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user
paged access (256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX
instruction (MOVX@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient
when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight
high ordered bits of address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct
access and two with paged access to the entire 64KB of external memory range.
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the 80515 core the standard data pointer is called DPTR, the second data
pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at
the LSB of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.
The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the
currently selected DPTR for any activity.
The second data pointer may or may not be supported by certain compilers.
The Internal data memory interface services up to 256 bytes of off-core data memory. The internal data memory
address is always 1 byte wide. The memory space is 256 bytes (00H to FFH), and can be accessed by either direct or
indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by
direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM.
The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of
eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16
bytes form a block of bit-addressable memory space at bit addressees 00H-7FH. All of the bytes in the lower 128 bytes
are accessible through direct or indirect addressing.
Table 6-3 shows the internal data memory map.
Revision 1.7
CKCON.2 CKCON.1
0
0
0
0
1
1
1
1
CKCON register
Dual Data Pointer
Internal Data Memory
0
0
1
1
0
0
1
1
CKCON.0
0
1
0
1
0
1
0
1
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Table 6-2: Stretch Memory Cycle Width
Stretch Value
0
1
2
3
4
5
6
7
TERIDIAN Proprietary
memaddr
Read signals width
1
2
3
4
5
6
7
8
memrd
1
2
3
4
5
6
7
8
71M652X Software User’s Guide
memaddr
Write signal width
2
3
4
5
6
7
8
9
memwr
1
1
2
3
4
5
6
7
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