71M6521FEIM-DB Maxim Integrated Products, 71M6521FEIM-DB Datasheet - Page 120

• Manufacturer Part Number: 71M6521FEIM-DB
• Description: Power Management Modules & Development Tools 71M6521FE DEMO BOARD M6521FE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FEIM-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The state of bits RS1 and RS0 select the working registers bank as follows:
The stack pointer is a 1-byte register initialized to 07H after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to begin at location 08H.
The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It is generally used to access external code
or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
The program counter (PC) is 2 bytes wide initialized to 0000H after reset. This register is incremented during the
fetching operation code or when operating on data from program memory.
Port registers ‘P0’, ‘P1’, and ‘P2’ are Special Function Registers. The contents of the SFR can be observed on
corresponding pins on the chip. Writing a ‘1’ to any of the ports causes the corresponding pin to be at high level (VCC),
and writing a ‘0’ causes the corresponding pin to be held at low level (GND).
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P2’), an output driver, and an
input buffer, therefore the MPU can output or read data through any of these ports if they are not used for alternate
purposes.
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter
or timer operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the
MPU clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin t0 or t1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
are used to select the appropriate mode.
Revision 1.7
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON)
Stack Pointer
Data Pointer
Program Counter
Ports
Timers 0 and 1
RS1/RS0
00
01
10
11
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Table 6-20: Register Bank Location
Bank selected
Bank 0
Bank 1
Bank 2
Bank 3
TERIDIAN Proprietary
Location
(00H – 07H)
(08H – 0FH)
(10H – 17H)
(18H – 1FH)
71M652X Software User’s Guide
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