ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 177

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.8.6
4.15.8.7
4921E–AUTO–09/09
Timer/Counter2 Interrupt Mask Register – TIMSK2
Timer/Counter2 Interrupt Flag Register – TIFR2
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
Read/Write
Initial Value
• Bit 2 – OCF2B: Output Compare Flag 2 B
• Bit 1 – OCF2A: Output Compare Flag 2 A
Initial Value
Read/Write
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2
Interrupt Flag Register – TIFR2.
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and
the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare
match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and
the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare
match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
Bit
Bit
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE2B
OCF2B OCF2A
R/W
ATA6602/ATA6603
R/W
2
0
2
0
OCIE2A
R/W
R/W
1
0
1
0
TOIE2
TOV2
R/W
R/W
0
0
0
0
TIMSK2
TIFR2
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