ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 191

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ATA6603-EK

Manufacturer Part Number
ATA6603-EK
Description
MCU, MPU & DSP Development Tools Demoboard LIN-MCM
Manufacturer
Atmel
Datasheet

Specifications of ATA6603-EK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4.17
4.17.1
4921E–AUTO–09/09
USART0
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
The USART can also be used in Master SPI mode (see
Power Reduction USART bit, PRUSART0, in
must be disabled by writing a logical zero to it.
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
“Power Reduction Register - PRR” on page 64
“USART in SPI Mode” on page
ATA6602/ATA6603
Figure 4-69 on page
192. CPU
218. The
191

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