ITG-3200 INVENSENSE, ITG-3200 Datasheet - Page 19

• Manufacturer Part Number: ITG-3200
• Description: IC, GYRO, TRI-AXIS, +/-2000 DEG/S
• Manufacturer: INVENSENSE

Specifications of ITG-3200

• No. Of Axes: 3
• Sensor Case Style: QFN
• No. Of Pins: 24
• Supply Voltage Range: 2.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Interface: I2C, Serial
• Interface Type: I2C, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Format / Acknowledge
I
Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is
generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding
it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can
hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and
releases the clock line (see figure below).
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an
8
device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.
Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line
LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with
a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START
condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on
the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with
the exception of start and stop conditions.
2
th
C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per data transfer.
bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave
TRANSMITTER (SDA)
DATA OUTPUT BY
DATA OUTPUT BY
SDA
SCL
RECEIVER (SDA)
condition
SCL FROM
START
MASTER
S
ADDRESS
1 – 7
condition
START
R/W
8
ITG-3200 Product Specification
ACK
9
Acknowledge on the I
Complete I
1
1 – 7
DATA
2
C Data Transfer
8
2
2
C Bus
ACK
9
1 – 7
not acknowledge
DATA
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
acknowledge
8
8
acknowledgement
clock pulse for
ACK
9
19 of 39
9
condition
STOP
P