AD6634BBCZ Analog Devices Inc, AD6634BBCZ Datasheet - Page 36

• Manufacturer Part Number: AD6634BBCZ
• Description: Pb-free Quad Receive Signal Processor
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6634
Note that Bit 0 = 1 Bit 1 = 0, and Bit 2 = 1 is not a valid
configuration. Bit 2 must be set to 0 to output AGC A IQ and
RSSI words on link port A, and AGC B IQ and RSSI words
on link port B.
Link Port Timing
Both link ports run off of PCLK, which can be externally provided
to the chip (Addr 0x1E Bit 0 = 0) or generated from the master
clock of the AD6634 (Addr 0x1E Bit 0 = 1). This register boots
to 0 (Slave mode) and allows the user to control the data rate
coming from the AD6634. PCLK can be run as fast as 100 MHz.
The link port provides a 1-byte data-word (LA[7:0], LB[7:0]
pins) and output clocks (LACLKOUT, LBCLKOUT pins) in
response to a ready signals (LACLKIN, LBCLKIN pins) from
the receiver. Each link port transmits eight bits on each edge of
LCLKOUT, requiring eight LCLKOUT cycles to complete
transmission of the full 16 bytes of a TigerSHARC quad-word.
Due to the TigerSHARC link port protocol, the AD6634 must
wait at least six PCLK cycles after the TigerSHARC is ready to
receive data, as indicated by the TigerSHARC setting the respective
AD6634 LCLKIN pin high. Once the AD6634 link port has
waited the appropriate number of PCLK cycles and has begun
transmitting data, the TigerSHARC does a connectivity check
by sending the AD6634 LCLKIN low and then high while the
data is being transmitted. This tells the AD6634 link port that the
TigerSHARC’s DMA is ready to receive the next quad-word after
completion of the current quad-word. Because the connectivity
check is done in parallel to the data transmission, the AD6634
is able to stream uninterrupted data to the TigerSHARC.
LCLKOUT
LDAT[7:0]
LINK PORT A
LINK PORT B
LCLKIN
LINK PORT
LINK PORT
A OR B
A OR B
TigerSHARC READY TO
RECEIVE QUAD-WORD
Figure 42. Link Port Data from AGC
Figure 43. Link Port Data Transfer
WAIT >= 6 CYCLES
AGC A I, Q
AGC A I, Q
AGC A I, Q
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0
AGC A RSSI
AGC B RSSI
AGC A RSSI
(4 BYTES)
(4 BYTES)
AGC B I, Q
(4 BYTES)
(4 BYTES)
D0 D1 D2 D3 D4
AGC A I, Q
AGC B I, Q
AGC A I, Q
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
RECEIVE NEXT QUAD-WORD
TigerSHARC READY TO
NEXT QUAD-WORD
AGC B RSSI
AGC B RSSI
AGC A RSSI
D15
(4 BYTES)
(4 BYTES)
(4 BYTES)
AGC B I, Q
(4 BYTES)
D0 D1 D2
–36–
The length of the wait before data transmission is a 4-bit
programmable value in the link port control registers (0x1B and
0x1D Bits 6–3). This value allows the AD6634 PCLK and
the TigerSHARC PCLK to be run at different rates and
out of phase.
WAIT ensures that the amount of time the AD6634 needs to wait
to begin data transmission is at least equal to the minimum amount
of time the TigerSHARC is expecting it to wait. If the PCLK of
the AD6634 is out of phase with the PCLK of the TigerSHARC
and the argument to the ceil() function is an integer, WAIT must
be strictly greater than the value given in the above formula.
If the LCLKs are in phase, the maximum output data rate is:
otherwise it is:
TigerSHARC Configuration
Since the AD6634 is always the transmitter in this link and the
TigerSHARC is always the receiver, the values in Table IX can
be programmed into the LCTL register for the link port used to
receive AD6634 output data. User means that the actual register
value depends on the user’s application.
MEMORY MAPS
0x00–0x7F: Coefficient Memory(CMEM)
This is the Coefficient Memory(C-MEM) used by the RCF
(See Table X). It is memory mapped as 128 words by 20 bits.
A second 128 words of RAM may be accessed via this same
location by writing Bit 8 of the RCF control register high at
channel address 0xA4. The filter calculated will always use the
same coefficients for I and Q. By using memory from both of these
128 blocks, a filter up to 160 taps can be calculated. Multiple
filters can be loaded and selected with a single internal access
to the Coefficient Offset register at channel address 0xA3.
Table IX. TigerSHARC LCTLx Register Configuration
WAIT
f
f
LCLK
LCLK
VERE
SPD
LTEN
PSIZE
TTOE
CERE
LREN
RTOE
_
≥
_
34
34
ceil
≤
≤
14



15
6
6
6
×
×
×
f
f
f
LCLK TSHARC
LCLK TSHARC
LCLK TSHARC
f
LCLK
_
_
_
0
User
0
1
0
0
1
1
_
34



REV. 0