AD6634BBCZ Analog Devices Inc, AD6634BBCZ Datasheet - Page 48

• Manufacturer Part Number: AD6634BBCZ
• Description: Pb-free Quad Receive Signal Processor
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6634
MICROPORT CONTROL
The AD6634 has an 8-bit microprocessor port and a serial control
port. The use of each of these ports is described separately below.
The interaction of the ports is then described. The microport
interface is a multimode interface that is designed to give flexibility
when dealing with the host processor. There are two modes
of bus operation: Intel Nonmultiplexed mode (INM), and
Motorola Nonmultiplexed mode (MNM). The mode is selected
based on host processor and which mode is best suited to that
processor. The microport has an 8-bit databus(D[7:0]), 3-bit
address bus(A[2:0]), three control pins lines (CS, DS, or RD, RW
or WR), and one status pin (DTACK or RDY). The functionality
of the control signals and status line changes slightly depending
upon the mode that is chosen. Refer to the timing diagrams and the
following descriptions for details on the operation of both modes.
External Memory Map
The External Memory Map is used to gain access to the channel
address space described previously. The 8-bit data and address
buses are used to this set of eight registers that can be seen in
Table XVI. These registers are collectively referred to as the
External Interface registers since they control all accesses to the
Channel Address space as well as input/output control registers.
The use of each of these individual registers is described in
detail. It should be noted that the Serial Control interface has
the same memory map as the microport interface and can carry
out the exact same functions, although at a slower rate.
A[2:0]
111
110
101
100
011
010
001
000
Name
Access Control Register (ACR)
Channel Address Register (CAR)
SOFT_SYNC Control Register (Write Only)
PIN_SYNC Control Register (Write Only)
SLEEP (Write Only)
Data Register 2 (DR2)
Data Register 1 (DR1)
Data Register 0 (DR0)
Table XVI. External Memory Map
–48–
Access Control Register (ACR)
The Access Control register serves to define the channel or
channels that receive an access from the microport or serial
port control.
Bit 7 of this register is the Auto-Increment bit. If this bit is a 1,
the CAR register described below will increment its value after
every access to the channel. This allows blocks of address space
such as coefficient memory to be initialized more efficiently.
Bit 6 of the register is the Broadcast bit and determines how
Bits 5–2 are interpreted. If Broadcast is 0, then Bits 5–2, which are
referred to as Instruction bits (Instruction[3:0]), are compared
with the CHIP_ID[3:0] pins. The instruction that matches the
CHIP_ID[3:0] pins will determine the access. This allows up to
16 chips to be connected to the same port and memory mapped
without external logic. This also allows the same serial port of a
host processor to configure up to 16 chips. If the Broadcast bit is
high, the Instruction[3:0] word allows multiple AD6634 channels
and/or chips to be simultaneously configured independent of the
CHIP_ID[3:0] pins. There are 10 possible instructions defined
in Table XVI. This is useful for smart antenna systems, where
multiple channels listing to a single antenna or carrier can be
configured simultaneously. The x(s) in the table represent don’t
cares in the digital decoding.
Comment
7:
6:
5–2:
1–0:
6:
5:
4:
3:
2:
1:
0:
7:
6:
5:
4:
3:
2:
1:
0:
5:
4:
3:
2:
1:
0:
3–0:
7–0:
7:
7–6:
7–4:
15–8: D[15:8]
7–0:
Auto Increment
Broadcast
Instruction[3:0]
A[9:8]
A[7:0]
PN_EN
Test_MUX_Select
Hop
Start
SYNC D
SYNC C
SYNC B
SYNC A
Toggle IEN for BIST
First SYNC Only
Hop_En
Start_En
SYNC_EN D
SYNC_EN C
SYNC_EN B
SYNC_EN A
Reserved
Access Input/Output Control Registers
Reserved low
SLEEP 3
SLEEP 2
SLEEP 1
SLEEP 0
Reserved
D[19:16]
D[7:0]
REV. 0