AD6634BBCZ Analog Devices Inc, AD6634BBCZ Datasheet - Page 51

• Manufacturer Part Number: AD6634BBCZ
• Description: Pb-free Quad Receive Signal Processor
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The AD6634 supports a subset of IEEE Standard 1149.1 speci-
fication. For additional details of the standard, please see “IEEE
Standard Test Access Port and Boundary-Scan Architecture,”
IEEE-1149 publication from IEEE.
The AD6634 has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port and
are listed in Table XVIII. All input JTAG pins are pull-up
except for TCLK, which is a pull-down.
Name
TRST
TCLK
TMS
TDI
TDO
The AD6634 supports six op codes as shown in Table XIX.
These instructions set the mode of the JTAG interface.
The Vendor Identification Code can be accessed through the
IDCODE instruction and has the format shown in Table XX.
MSB
Version
0000
A BSDL file for this device is available. Please contact Analog
Devices for more information.
REV. 0
JTAG BOUNDARY SCAN
FRAME
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
HIGHZ
CLAMP
SCLK
Instruction
Table XVIII. Boundary Scan Test Pins
SDI
Table XIX. Boundary Scan Op Codes
Part
Number
0010
0111
1000
1100
Pin Number
67
68
69
72
70
Table XX. Vendor ID Code
X
X
Manufacturing
ID #
000 1110 0101
Figure 47. Serial Word Structure and Serial Port Control Timing
Test Access Port Reset
Test Clock
Test Access Port Mode Select
Test Data Input
Test Data Output
Description
X
X
Op Code
001
111
010
000
011
100
A2
LSB
Mandatory
1
t
SSI
A1
FRAME
A0
–51–
EXTEST (3'b000)—Places the IC into an external boundary-test
mode and selects the boundary-scan register to be connected
between TDI and TDO. During this, the boundary-scan register
is accessed to drive test data off-chip via boundary outputs and
receive test data off-chip from boundary inputs.
IDCODE (3'b001)—Allows the IC to remain in its functional
mode and selects device ID register to be connected between TDI
and TDO. Accessing the ID register does not interfere with the
operation of the IC.
SAMPLE/PRELOAD (3'b010)—Allows the IC to remain in
normal functional mode and selects the boundary-scan register
to be connected between TDI and TDO. The boundary-scan
register can be accessed by a scan operation to take a sample of
the functional data entering and leaving the IC. Also, test data
can be preloaded into the boundary scan register before an
EXTEST instruction.
HIGHZ (3'b011)—Sets all outputs to high impedance state. Selects
1-bit bypass register to be connected between TDI and TDO.
CLAMP (3'b100)—Sets the outputs of the IC to logic levels
determined by the boundary-scan register and selects 1-bit bypass
register to be connected between TDI and TDO. Before this
instruction, boundary-scan data can be preloaded with the
SAMPLE/PRELOAD instruction.
BYPASS (3'b111)—Allows the IC to remain in normal functional
mode and selects 1-bit bypass register between TDI and TDO.
During this instruction, serial data is transferred from TDI to TDO
without affecting operation of the IC.
INTERNAL WRITE ACCESS
Up to 20 bits of data (as needed) can be written by the process
described below. Any high order bytes that are needed are written
to the corresponding data registers defined in the external 3-bit
address space. The least significant byte is then written to DR0
at address (000). When a write to DR0 is detected, the internal
microprocessor port state machine then moves the data in
DR2–DR0 to the internal address pointed to by the address in
the LAR and AMR.
Write Pseudocode
void write_micro(ext_address, int data);
main();
{
/* This code shows the programming of the NCO phase offset
register using the write_micro function as defined above. The
variable address is the External Address A[2:0] and data is the
value to be placed in the external interface register.
D7
CLKn
D6
D5
D4
X
D3
D2
D1
AD6634
D0