AD7656BSTZ-1 Analog Devices Inc, AD7656BSTZ-1 Datasheet - Page 23

• Manufacturer Part Number: AD7656BSTZ-1
• Description: 6-CHANNEL 16-BIT SE BIPOLAR I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7656BSTZ-1

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7656-1EDZ - BOARD EVAL CONTROL AD7656-1EVAL-AD7656-1CBZ - BOARD EVAL FOR AD7656-1EVAL-AD7656CBZ - BOARD EVAL FOR AD7656
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The CS signal can be permanently tied low, and the RD signal
can be used to access the conversion results. A read operation
can take place after the BUSY signal goes low. The number of
required read operations depends on the number of ADCs that
are simultaneously sampled (see
and CONVST B are simultaneously brought low, four read
operations are required to obtain the conversion results from
V1, V2, V3, and V4. If CONVST A and CONVST C are
simultaneously brought low, four read operations are required
to obtain the conversion results from V1, V2, V5, and V6.
The conversion results are output in ascending order. For
the AD7657-1, DB15 and DB14 contain two leading 0s, and
DB[13:0] output the 14-bit conversion result. For the AD7658-1,
DB[15:12] contain four leading 0s, and DB[11:0] output the
12-bit conversion result.
When using the three CONVST signals to independently
initiate conversions on the three ADC pairs, care should be
taken to ensure that a conversion is not initiated on a channel
pair when the BUSY signal is high. It is also recommended not
to initiate a conversion during a read sequence because doing so
CONVST A,
CONVST B,
CONVST C
BUSY
DATA
CS
RD
DB15 TO DB8
t
CONV
RD
CS
Figure 29. Parallel Interface—Read Cycle for Byte Mode of Operation. ( W /B = 1, HBEN = 0)
Figure 28
t
2
t
3
). If CONVST A
V1
Figure 28. Parallel Interface Timing Diagram ( W /B = 0)
t
4
t
3
t
t
V2
5
6
LOW BYTE
t
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5
t
6
t
7
t
V3
t
8
4
may affect the performance of the conversion. For the specified
performance, it is recommended to perform the read after the
conversion. For unused input channel pairs, the associated
CONVST pin should be tied to V
If there is only an 8-bit bus available, the AD7656-1/AD7657-1/
AD7658-1 parallel interface can be configured to operate in byte
mode ( W /B = 1). In this configuration, the DB7/HBEN/DCEN
pin takes on its HBEN function. Each channel conversion result
from the AD7656-1/AD7657-1/AD7658-1 can be accessed in
two read operations, with eight bits of data provided on DB15
to DB8 for each of the read operations (see
HBEN pin determines whether the read operation first accesses
the high byte or the low byte of the 16-bit conversion result. To
always access the low byte first on DB15 to DB8, the HBEN pin
should be tied low. To always access the high byte first on DB15
to DB8, the HBEN pin should be tied high. In byte mode when
all three CONVST pins are pulsed together to initiate simultaneous
conversions on all six ADCs, 12 read operations are necessary
to read back the six 16-/14-/12-bit conversion results. DB[6:0]
should be left unconnected in byte mode.
t
9
t
ACQ
t
9
V4
t
7
AD7656-1/AD7657-1/AD7658-1
V5
HIGH BYTE
t
8
V6
DRIVE
.
t
QUIET
Figure 29
t
10
). The