AD7656BSTZ-1 Analog Devices Inc, AD7656BSTZ-1 Datasheet - Page 25

• Manufacturer Part Number: AD7656BSTZ-1
• Description: 6-CHANNEL 16-BIT SE BIPOLAR I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7656BSTZ-1

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7656-1EDZ - BOARD EVAL CONTROL AD7656-1EVAL-AD7656-1CBZ - BOARD EVAL FOR AD7656-1EVAL-AD7656CBZ - BOARD EVAL FOR AD7656
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Changing the Analog Input Range ( H /S SEL = 0)
The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the
user to select either ±2 × V
range for the six analog inputs. When the H /S SEL pin is low,
the logic state of the RANGE pin is sampled on the falling edge of
the BUSY signal to determine the range for the next simultaneous
conversion. When the RANGE pin is logic high at the falling
edge of the BUSY signal, the range for the next conversion is
±2 × V
edge of the BUSY signal, the range for the next conversion is
±4 × V
falling BUSY edge.
Changing the Analog Input Range ( H /S SEL = 1)
When the H /S SEL pin is high, the range can be changed by
writing to the control register. DB[12:10] in the control register
are used to select the analog input ranges for the next conversion.
Each analog input pair has an associated range bit, allowing
independent ranges to be programmed on each ADC pair.
When the RNGx bit is set to 1, the range for the next conversion
is ±2 × V
conversion is ±4 × V
Serial Interface (SER/ PAR SEL = 1)
By pulsing one, two, or all three CONVST signals, the AD7656-1/
AD7657-1/AD7658-1 use their on-chip trimmed oscillator to
simultaneously convert the selected channel pairs on the rising
edge of CONVST. After the rising edge of CONVST, the BUSY
signal goes high to indicate that the conversion has started. It
returns low when the conversion is complete, 3 μs later. The
output register is loaded with the new conversion results, and
data can be read from the AD7656-1/AD7657-1/AD7658-1.
To read the data back from the parts over the serial interface,
SER/ PAR SEL should be tied high. The CS and SCLK signals are
used to transfer data from the AD7656-1/AD7657-1/AD7658-1.
The parts have three DOUT pins: DOUT A, DOUT B, and
DOUT C. Data can be read back from each part using one, two,
or all three DOUT lines.
Figure 31 shows six simultaneous conversions and the read
sequence using three DOUT lines. Also in Figure 31, 32 SCLK
transfers are used to access data from the AD7656-1/AD7657-1/
AD7658-1; however, two 16-SCLK individually framed transfers
with the CS signal can also be used to access the data on the
three DOUT lines. When the serial interface is selected and
conversion data is clocking out on all three DOUT lines,
DB0/SEL A, DB1/SEL B, and DB2/SEL C should be tied to
V
lines, respectively.
DRIVE
. These pins are used to enable the DOUT A to DOUT C
REF
REF
REF
. When the RANGE pin is logic low at the falling
. After a RESET pulse, the range is updated on the first
. When the RNGx bit is set to 0, the range for the next
REF
.
REF
or ±4 × V
REF
as the analog input
Rev. 0 | Page 25 of 32
If it is required to clock conversion data out on two data output
lines, DOUT A and DOUT B should be used. To enable DOUT A
and DOUT B, DB0/SEL A and DB1/SEL B should be tied to V
and DB2/SEL C should be tied low. When six simultaneous
conversions are performed and only two DOUT lines are used,
a 48 SCLK transfer can be used to access the data from the
AD7656-1/AD7657-1/AD7658-1. The read sequence is shown
in Figure 32 for a simultaneous conversion on all six ADCs
using two DOUT lines. If a simultaneous conversion occurred
on all six ADCs, and only two DOUT lines are used to read the
results from the AD7656-1/AD7657-1/AD7658-1. DOUT A
clocks out the result from V1, V2, and V5, whereas DOUT B
clocks out the results from V3, V4, and V6.
Data can also be clocked out using just one DOUT line, in which
case DOUT A should be used to access the conversion data. To
configure the AD7656-1/AD7657-1/AD7658-1 to operate in
this mode, DB0/SEL A should be tied to V
and DB2/SEL C should be tied low. The disadvantage of using
only one DOUT line is that the throughput rate is reduced. Data
can be accessed from the AD7656-1/AD7657-1/AD7658-1 using
one 96 SCLK transfer, three 32-SCLK individually framed transfers,
or six 16-SCLK individually framed transfers. When using the
serial interface, the RD signal should be tied low and the unused
DOUT line(s) should be left unconnected.
Serial Read Operation
Figure 33 shows the timing diagram for reading data from the
AD7656-1/AD7657-1/AD7658-1 when the serial interface is
selected. The SCLK input signal provides the clock source for
the serial interface. The CS signal goes low to access data from
the AD7656-1/AD7657-1/AD7658-1. The falling edge of CS
takes the bus out of three-state and clocks out the MSB of the
16-bit conversion result. The ADCs output 16 bits for each
conversion result; the data stream of the AD7656-1 consists of
16 bits of conversion data, provided MSB first. The data stream
for the AD7657-1 consists of two leading 0s followed by 14 bits
of conversion data, provided MSB first. The data stream for the
AD7658-1 consists of four leading 0s and 12 bits of conversion
data, provided MSB first.
The first bit of the conversion result is valid on the first SCLK
falling edge after the CS falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion result,
16 clock pulses must be provided to the AD7656-1/AD7657-1/
AD7658-1.
access the conversion results.
Figure 33
AD7656-1/AD7657-1/AD7658-1
shows how a 16-SCLK read is used to
DRIVE
, and DB1/SEL B
DRIVE
,