AD7707BR Analog Devices Inc, AD7707BR Datasheet - Page 10

• Manufacturer Part Number: AD7707BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7707BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: 3V/5V, 1mW, 2?Channel, 16?Bit
• Package / Case: 20-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7707
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Mnemonic
SCLK
MCLK IN
MCLK OUT
CS
RESET
AV
AIN1
LOCOM
AIN2
AIN3
HICOM
VBIAS
REF IN(+)
REF IN(−)
AGND
DRDY
DOUT
DD
Description
Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data
from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of
pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in
smaller batches of data.
Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock
frequencies in the range of 500 kHz to 5 MHz.
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock
can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user
does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the
part is not wasting unnecessary power driving capacitive loads on MCLK OUT.
Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the
AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame
synchronization signal in communicating with the AD7707.
Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and
analog modulator of the part to power-on status.
Analog Supply Voltage, 2.7 V to 5.25 V Operation.
Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM.
Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input.
Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM.
Single-Ended High Level Analog Input Channel with respect to HICOM.
Common Input for igh evel nput hannel. Analog input on AIN3 must be referenced to this input.
VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and
AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected
to 2.5 V when AV
Reference Input. Positive input of the differential reference input to the AD7707. The reference input is
differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between
AV
Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere
between AV
Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data
register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has
taken place between output updates, the DRDY line returns high for 500 × t
update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from
the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY
is also used to indicate when the AD7707 has completed its on-chip calibration sequence.
Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift
register can contain information from the setup register, communications register, clock register, or data register,
depending on the register selection bits of the communications register.
DD
and AGND.
DD
and AGND provided that REF IN(+) is greater than REF IN(−).
DD
= 5 V and 1.225 V when AV
MCLK OUT
MCLK IN
LOCOM
RESET
SCLK
AV
AIN1
AIN2
AIN3
CS
DD
Figure 3. Pin Configuration
Rev. B | Page 10 of 52
10
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD7707
TOP VIEW
DD
= 3 V.
20
19
18
17
16
15
14
13
12
11
DGND
DV
DIN
DOUT
DRDY
AGND
REF IN(–)
REF IN(+)
VBIAS
HICOM
DD
CLK IN
cycles prior to the next output