AD7707BR Analog Devices Inc, AD7707BR Datasheet - Page 34

• Manufacturer Part Number: AD7707BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7707BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: 3V/5V, 1mW, 2?Channel, 16?Bit
• Package / Case: 20-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7707
Because the FSYNC bit resets the digital filter, the full settling
time of 3 × 1/output rate has to elapse before there is a new
word loaded to the output register on the part. If the DRDY
signal is low when FSYNC goes to a 0, the DRDY signal is not
reset high by the FSYNC command. This is because the
AD7707 recognizes that there is a word in the data register that
has not been read. The DRDY line stays low until an update of
the data register takes place, at which time it goes high for 500 ×
t
resets the DRDY signal high and it does not return low until the
settling time of the filter has elapsed (from the FSYNC command)
and there is a valid new word in the data register. If the DRDY
line is high when the FSYNC command is issued, the DRDY
line does not return low until the settling time of the filter has
elapsed.
RESET INPUT
The RESET input on the AD7707 resets all the logic, the digital
filter, and the analog modulator, while all on-chip registers are
reset to their default state. DRDY is driven high and the AD7707
ignores all communications to any of its registers while the RESET
input is low. When the RESET input returns high, the AD7707
starts to process data and DRDY returns low in 3 × 1/output
rate, indicating a valid new word in the data register. However,
the AD7707 operates with its default setup conditions after a
RESET and it is generally necessary to set up all registers and
carry out a calibration after a RESET command.
The AD7707’s on-chip oscillator circuit continues to function
even when the RESET input is low. The master clock signal
continues to be available on the MCLK OUT pin. Therefore, in
applications where the system clock is provided by the AD7707’s
clock, the AD7707 produces an uninterrupted master clock
during RESET commands.
STANDBY MODE
The STBY bit in the communications register of the AD7707
allows the user to place the part in a power-down mode when it
is not required to provide conversion results. The AD7707
retains the contents of all its on-chip registers (including the
data register) while in standby mode. When released from
standby mode, the part starts to process data and a new word is
available in the data register in 3 × 1/output rate from when a 0
is written to the STBY bit.
The STBY bit does not affect the digital interface, nor does it
affect the status of the DRDY line. If DRDY is high when the
STBY bit is brought low, it remains high until there is a valid
new word in the data register. If DRDY is low when the STBY
bit is brought low, it remains low until the data register is
updated, at which time the DRDY line returns high for 500 ×
CLKIN
before returning low again. A read from the data register
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t
enters its standby mode (indicating a valid unread word in the
data register), the data register can be read while the part is in
standby. At the end of this read operation, the DRDY is reset
high as normal.
Placing the part in standby mode reduces the total current to
9 μA typical with 5 V supplies and 4 μA with 3 V supplies when
the part is operated from an external master clock provided this
master clock is stopped. If the external clock continues to drive
the MCLK IN pin in standby mode, the standby current increases
to 150 μA typical with 5 V supplies and 75 μA typical with 3 V
supplies. If a crystal or ceramic resonator is used as the clock
source, the total current in standby mode is 400 μA typical with
5 V supplies and 90 μA with 3 V supplies. This is because the
on-chip oscillator circuit continues to run when the part is in its
standby mode. This is important in applications where the system
clock is provided by the AD7707’s clock, so that the AD7707
produces an uninterrupted master clock even when it is in its
standby mode. The serial interface remains operational when in
standby mode so that data can be read from the output register
in standby, regardless of whether or not the master clock is stopped.
ACCURACY
Σ-Δ ADCs, like voltage–to-frequency converters (VFCs) and
other integrating ADCs, do not contain any source of
nonmonotonicity and inherently offer no missing codes
performance. The AD7707 achieves excellent linearity by the
use of high quality, on-chip capacitors that have a very low
capacitance/voltage coefficient. The device also achieves low
input drift through the use of chopper-stabilized techniques in
its input stage. To ensure excellent performance over time and
temperature, the AD7707 uses digital calibration techniques
that minimize offset and gain error.
DRIFT CONSIDERATIONS
Charge injection in the analog switches and dc leakage currents
at the sampling modes are the primary sources of offset voltage
drift in the converter. The dc input leakage current is essentially
independent of the selected gain. Gain drift within the converter
depends primarily upon the temperature tracking of the internal
capacitors. It is not affected by leakage currents.
Measurement errors due to offset drift or gain drift can be
eliminated at any time by recalibrating the converter. Using the
system calibration mode can also minimize offset and gain errors
in the signal conditioning circuitry. Integral and differential
linearity errors are not significantly affected by temperature
changes.
CLKIN
before returning low again. If DRDY is low when the part