AD9231BCPZ-20 Analog Devices Inc, AD9231BCPZ-20 Datasheet - Page 25

• Manufacturer Part Number: AD9231BCPZ-20
• Description: 12 Bit, 20 MSPS Dual Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9231BCPZ-20

• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 73.3mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
jitter (t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 56.
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9231.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note available on www.analog.com.
CHANNEL/CHIP SYNCHRONIZATION
The AD9231 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
SNR
80
75
70
65
60
55
50
45
JRMS
1
HF
) can be calculated by
= −10 log[(2π × f
Figure 56. SNR vs. Input Frequency and Jitter
LF
) at a given input frequency (f
10
FREQUENCY (MHz)
INPUT
× t
JRMS
)
100
2
+ 10
3.0ps
(
−
SNR
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
INPUT
LF
/
10
) due to
)
1k
]
Rev. A | Page 25 of 36
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the analog core power dissipated by
the AD9231 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
where N is the number of output bits (26, in the case of the
AD9231).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
IDRVDD = V
150
130
110
90
70
50
0
CLK
Figure 57. Analog Core Power vs. Clock Rate
10
/2. In practice, the DRVDD current is estab-
DRVDD
AD9231-20
20
× C
CLOCK RATE (MSPS)
AD9231-40
30
LOAD
× f
40
CLK
AD9231-65
× N
50
60
AD9231-80
70
AD9231
8
0