AD9231BCPZ-20 Analog Devices Inc, AD9231BCPZ-20 Datasheet - Page 31

• Manufacturer Part Number: AD9231BCPZ-20
• Description: 12 Bit, 20 MSPS Dual Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9231BCPZ-20

• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 73.3mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x05
0xFF
Program Registers (May or May Not Be Indexed by Device Index)
0x08
0x09
0x0B
0x0D
Register
Name
SPI port
configuration
(global)
Chip ID (global)
Chip grade
(global)
Channel index
Transfer
Modes
Clock (global)
Clock divide
(global)
Test mode (local)
Bit 7
(MSB)
0
8-bit chip ID bits [7:0]
AD9231 = 0x24
Open
Open
Open
External
power-
down
enable
(local)
Open
Open
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
Bit 6
LSB
first
Speed grade ID [6:4]
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open
Open
External pin function
0x00 full power-down
0x01 standby
(local)
Open
Bit 5
Soft reset
Open
Open
Open
Reset PN
long gen
Rev. A | Page 31 of 36
Bit 4
1
Open
Open
Open
Reset
PN
short
gen
Open
Bit 3
1
Open
Open
Open
Open
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1x sync
1011 = one bit high
1100 = mixed bit frequency
Bit 2
Soft
reset
Open
Open
Clock divider [2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB
first
ADC B
default
Open
00 = chip run
01 = full power-
down
10 = standby
11 = chip wide
digital reset (local)
Open
Bit 0
(LSB)
0
ADC A
default
Transfer
Duty
cycle
stabilize
Default
Value
(Hex)
0x18
0x03
0x00
0x80
0x00
0x00
0x00
Comments
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regardless
of shift mode
Unique chip ID used
to differentiate
devices; read only
Unique speed
grade ID used to
differentiate
devices; read only
Bits are set to
determine which
device on chip
receives the next
write command;
the default is all
devices on chip
Synchronously
transfers data from
the master shift
register to the slave
Determines various
generic modes of
chip operation
The divide ratio is
the value plus 1
When set, the test
data is placed on
the output pins in
place of normal
data
AD9231