AD9231BCPZ-20 Analog Devices Inc, AD9231BCPZ-20 Datasheet - Page 32

• Manufacturer Part Number: AD9231BCPZ-20
• Description: 12 Bit, 20 MSPS Dual Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9231BCPZ-20

• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 73.3mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9231
Addr
(Hex)
0x0E
0x10
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
0x2A
0x2E
Register
Name
BIST enable
Offset adjust
(local)
Output mode
OUTPUT_ADJUST
OUTPUT_PHASE
OUTPUT_DELAY
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
Features
Output assign
Bit 7
(MSB)
Open
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO
output
polarity
0 =
normal
1 =
inverted
(local)
Enable
DCO
delay
B7
B15
B7
B15
Open
Open
Bit 6
Open
Open
Open
B6
B14
B6
B14
Open
Open
Bit 5
Open
Output mux
enable
(interleaved)
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
Open
Enable
data
delay
B5
B13
B5
B13
Open
Open
BIST signature [7:0]
Rev. A | Page 32 of 36
Bit 4
Open
Output
disable
(local)
Open
Open
B4
B12
B4
B12
Open
Open
Bit 3
Open
Open
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Open
Open
B3
B11
B3
B11
Open
Open
Bit 2
BIST
INIT
Output
invert
(local)
Input clock phase adjust [2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/Data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
B2
B10
B2
B10
Open
Open
Bit 1
Open
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
B1
B9
B1
B9
Open
Open
Bit 0
(LSB)
BIST
enable
B0
B8
B0
B8
OR OE
(local)
0 =
ADC A
1 =
ADC B
(local)
Default
Value
(Hex)
0x00
0x00
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Ch A =
0x00
Ch B =
0x01
Comments
When Bit 0 is set,
the BIST function is
initiated
Device offset trim
Configures the
outputs and the
format of the data
Determines
CMOS output drive
strength properties
On devices that
utilize global clock
divide, this register
determines which
phase of the divider
output is used to
supply the output
clock; internal
latching is
unaffected
This sets the fine
output delay of the
output clock but
does not change
internal timing
pattern, 1 LSB
pattern, 1 MSB
pattern, 2 LSB
pattern, 2 MSB
Least significant
byte of BIST
signature, read only
Disable the OR pin
for the indexed
channel
Assign an ADC to an
output channel
User-defined
User-defined
User-defined
User-defined