AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 32

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9980
0x18
Table 31. Clamp Source Selection Settings
Clamp Source
0
1
0x18
Table 32. Red Clamp Select Settings
Clamp
0
1
0x18
Table 33. Green Clamp Select Settings
Clamp
0
1
0x18
Table 34. Blue Clamp Select Settings
Clamp
0
1
0x19
4
This bit determines the source of clamp timing. A 0
enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp posi-
tion and duration is counted from the leading edge of
Hsync. A 1 enables the external clamp input pin. The
three channels are clamped when the clamp signal is
active. The polarity of clamp is determined by the
clamp polarity bit. The power-up default setting
is 0.
3
This bit determines whether the red channel is
clamped to ground or to midscale. The power-up
default setting is 0.
2
This bit determines whether the green channel is
clamped to ground or to midscale. The power-up
default setting is 0.
1
This bit determines whether the blue channel is
clamped to ground or to midscale. The power-up
default setting is 0.
7:0
An 8-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp
signal is generated internally at a position established
by the clamp placement register (0x19) and for a
duration set by the clamp duration register (0x1A).
Clamping starts a clamp placement (Register 0x19)
count of pixel periods after the trailing edge of Hsync.
Result
Clamp to ground
Clamp to midscale
Clamp Source
Red Clamp Select
Green Clamp Select
Blue Clamp Select
Clamp Placement
Result
Internally generated clamp
Externally provided clamp signal
Result
Clamp to ground
Clamp to midscale
Result
Clamp to ground
Clamp to midscale
Rev. 0 | Page 32 of 44
0x1A
0x1B
Table 35. Clamp Polarity Override Settings
Override Bit
0
1
0x1B
Table 36. Clamp Polarity Override Settings
CLMPOL
0
1
The clamp placement may be programmed to
any value between 1 and 255. A value of 0 is
not supported.
The clamp should be placed during a time that the
input signal presents a stable black-level reference,
usually the back porch period between Hsync and the
image. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 8.
7:0
An 8-bit register that sets the duration of the
internally generated clamp.
When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp
signal is generated internally at a position established
by the clamp placement register and for a duration set
by the clamp duration register. Clamping begins a
clamp placement (Register 0x19) count of pixel peri-
ods after the trailing edge of Hsync. The clamp dura-
tion may be programmed to any value between 1 and
255. A value of 0 is not supported.
For the best results, the clamp duration should be set
to include the majority of the black reference signal
time that follows the Hsync signal trailing edge.
Insufficient clamping time can produce brightness
changes at the top of the screen, and a slow recovery
from large changes in the average picture level (APL),
or brightness. When EXTCLMP = 1, this register is
ignored. Power-up default setting is 20 DDR.
7
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The
power-up default setting is 0.
6
This bit indicates the polarity of the clamp signal only
if Bit 7 of Register 0x1B = 1. The power-up default
setting is 1.
Clamp Duration
Clamp Polarity Override
Input Clamp Polarity
Preliminary Technical Data
Result
Clamp polarity determined by chip
Clamp polarity determined by user
Register 0x1B, Bit 6
Result
Active low
Active high