ADC0808S125/DB NXP Semiconductors, ADC0808S125/DB Datasheet - Page 8
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ADC0808S125/DB
Manufacturer Part Number
ADC0808S125/DB
Description
ADC0808S125 Demo Board
Manufacturer
NXP Semiconductors
Series
-r
Specifications of ADC0808S125/DB
Design Resources
ADC0808S Demo Brd PCB Files
Number Of Adc's
1
Number Of Bits
8
Sampling Rate (per Second)
125M
Data Interface
Parallel
Input Range
2 Vpp
Power (typ) @ Conditions
240mW @ 125MSPS
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC0808S125
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
ADC0808S125_ADC0808S250_3
Product data sheet
7.5 Full-scale input selection
The ADC0808S has an internal reference circuit which can be overruled by an external
reference voltage. This can be done with the full-scale reference voltage (V
according to
The ADC provides the required common-mode voltage on pin CMADC. In case of internal
regulation, the regulator output voltage on pin CMADC is 0.95 V.
Table 9.
The internal reference circuit is enabled by connecting pin FSIN to ground. The
common-mode output voltage V
maximum peak-to-peak input voltage V
The ADC full-scale input selection principle is shown in
Full-scale reference voltage
V
1.15 V
1.20 V
1.25 V
1.30 V
1.35 V
Fig 6.
ref(fs)
Complete conversion signal timing diagram using CCS
Full-scale input selection
CCS (f
Table
CCS (f
D0 to D7
clk
/ 2)
clk
9.
)
Rev. 03 — 24 February 2009
Common-mode output
voltage V
0.8 V
0.86 V
0.94 V
1.01 V
1.09 V
O(cm)
n
data
2
on pin CMADC will then be 0.95 V, and the
O(cm)
i(p-p)(max)
t
d(CCS)
Single 8-bit ADC, up to 125 MHz or 250 MHz
n
data
1
will be 2.0 V; see
ADC0808S125/250
Figure
data
n
Maximum peak-to-peak input
voltage V
1.825 V
1.91 V
1.99 V
2.08 V
2.16 V
9.
Figure 7
n
data
001aab893
i(p-p)(max)
1
© NXP B.V. 2009. All rights reserved.
50 %
50 %
and
ref(fs)
Figure
)
8 of 23
8.