ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet - Page 12

• Manufacturer Part Number: ADCLK854/PCBZ
• Description: Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK854/PCBZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Embedded: No
• Utilized Ic / Part: ADCLK854
• Primary Attributes: 2 Inputs, 12 Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCLK854
FUNCTIONAL DESCRIPTION
The ADCLK854 accepts a clock input from one of two inputs
and distributes the selected clock to all output channels. The
outputs are grouped into three banks of four and can be set to
either LVDS or CMOS levels. This allows the selection of mul-
tiple logic configurations ranging from 12 LVDS to 24 CMOS
outputs, along with other combinations using both types of logic.
CLOCK INPUTS
The ADCLK854 differential inputs are internally self-biased.
The clock inputs have a resistor divider that sets the common-
mode level for the inputs. The complementary inputs are biased
about 30 mV lower than the true input to avoid oscillations if
the input signal stops. See Figure 20 for the equivalent input
circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays a
guide for input logic compatibility. A single-ended input can be
accommodated by ac or dc coupling to one side of the differential
input; bypass the other input to ground with a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 11. See Figure 27 through Figure 32 for
different termination schemes.
AC-COUPLED INPUT APPLICATIONS
The ADCLK854 offers two options for ac coupling. The first
option requires no external components (excluding the dc
blocking capacitor), it allows the user to simply couple the
reference signal onto the clock input pins. For more infor-
mation, see Figure 29.
Table 8. Input Logic Compatibility
Supply (V)
3.3
2.5
1.8
3.3
2.5
1.8
1.5
3.3
2.5
1.8
CLKx
Figure 20. ADCLK854 Input Stage
9kΩ
9kΩ
Logic
CML
CML
CML
CMOS
CMOS
CMOS
HSTL
LVDS
LVPECL
LVPECL
LVPECL
10kΩ
10kΩ
9.5kΩ
8.5kΩ
Common Mode (V)
2.9
2.1
1.4
1.65
1.25
0.9
0.75
1.25
2.0
1.2
0.5
V
CLKx
GND
S
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Output Swing (V)
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
The second option allows the use of the V
bias level for the ADCLK854. The V
CLKx and CLKx through resistors. This method allows lower
impedance termination of signals at the ADCLK854 (for more
information, see Figure 32). The internal bias resistors remain
in parallel with the external biasing. However, the relatively
high impedance of the internal resistors allows the external
termination to V
when offsetting the inputs; using only the internal biasing, as
previously mentioned, is not desirable.
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two single-
ended CMOS outputs (always in phase). When the LVDS driver
is enabled, the corresponding CMOS driver is in tristate; when
the CMOS driver is enabled, the corresponding LVDS driver is
powered down and tristated. Figure 21 and Figure 22 display
the equivalent output stage.
Figure 21. LVDS Output Simplified Equivalent Circuit
Figure 22. CMOS Output Equivalent Circuit
REF
V
S
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
AC-Coupled
Not allowed
Not allowed
to dominate. This method is also useful
3.5mA
3.5mA
OUTA
V
S
REF
OUTx
OUTx
V
pin can be connected to
S
REF
OUTB
DC-Coupled
Not allowed
Not allowed
Yes
Not allowed
Not allowed
Yes
Yes
Yes
Not allowed
Yes
Yes
pin to set the dc