ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet - Page 15

• Manufacturer Part Number: ADCLK854/PCBZ
• Description: Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK854/PCBZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Embedded: No
• Utilized Ic / Part: ADCLK854
• Primary Attributes: 2 Inputs, 12 Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

still meet receiver input requirements in some applications. This
can be useful when driving long trace lengths on less critical
networks.
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The ADCLK854 offers LVDS outputs
that are better suited for driving long traces wherein the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
INPUT TERMINATION OPTIONS
For single-ended operation always bypass unused input to
GND, as shown in Figure 31.
Figure 32 illustrates the use of V
termination into V
input offset is with external resistor values; for example, using a
1.8 V CMOS with long traces to provide far end termination.
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration
Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration
Figure 27. CMOS Output with Far End Termination
CMOS
(See Table 8 for CML Coupling Limitations)
CLK
CLK
CLK
CLK
CLK
CLK
(See Table 8 for More Information)
S
/2. In addition, a way to negate the 30 mV
10Ω
100Ω
V
V
CC
CC
50Ω
REF
to provide low impedance
V
S
100Ω
100Ω
CMOS
Rev. 0 | Page 15 of 16
Figure 32. Use of V
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths
CLK
CLK
Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration
(See Table 8 for LVPECL DC-Coupling Limitations)
(See Table 8 for CMOS Compatibility)
CLK
CLK
CLK
CLK
CLK
CLK
REF
CLK
CLK
50Ω
50Ω
to Provide Low Impedance Termination into V
50Ω
50Ω
V
V
CC
CC
– 2V
– 2V
CLK
CLK
V
REF
ADCLK854
S
/2