ADF7020-1BCPZ-RL7 Analog Devices Inc, ADF7020-1BCPZ-RL7 Datasheet - Page 15

• Manufacturer Part Number: ADF7020-1BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ-RL7

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscil-
lator circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section (see Figure 19) and supplies a divided-down
50:50 mark-space signal to the CLKOUT pin. An even divide
from 2 to 30 is available. This divide number is set in R1_DB
(8:11). On power-up, the CLKOUT defaults to the divide-by-8
block.
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at F
OSC1
Figure 19. Oscillator Circuit on the ADF7020-1
OSC1
DIVIDER
1 TO 15
CP2
Figure 20. CLKOUT Stage
CP1
÷2
OSC2
DV
DD
CLK
.
CLKOUT
CLKOUT
ENABLE BIT
Rev. 0 | Page 15 of 48
R Counter
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
points in the ADF7020-1. The state of MUXOUT is controlled
by Bits R0_DB (29:31).
Regulator Ready
Regulator ready is the default setting on MUXOUT after the
transceiver has been powered up. The power-up time of the
regulator is typically 50 μs. Because the serial interface is
powered from the regulator, the regulator must be at its
nominal voltage before the ADF7020-1 can be programmed.
The status of the regulator can be monitored at MUXOUT.
When the regulator ready signal on MUXOUT is high,
programming of the ADF7020-1 can begin.
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
REGULATOR READY
PFD [Hz] = XTAL/R
PLL TEST MODES
Σ-Δ TEST MODES
Figure 21. MUXOUT Circuit
MUX
CONTROL
ADF7020-1
DGND
DV
DD
MUXOUT