ADF7020-1BCPZ-RL7 Analog Devices Inc, ADF7020-1BCPZ-RL7 Datasheet - Page 21

• Manufacturer Part Number: ADF7020-1BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ-RL7

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the base-band channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integra-
tor in feedback around the log amp. This uses the BB offset
clock divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is
reduced. When the RSSI is below AGC_LOW_THRESHOLD, the
gain is increased. A delay (AGC_DELAY) is programmed to allow
for settling of the loop. The user programs the two threshold values
(recommended defaults, 30 and 70) and the delay (default, 10).
The default AGC set-up values should be adequate for most
applications. The threshold values must be more than 30 settings
apart for the AGC to operate correctly.
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB (4:5) to give an offset clock between 1 MHz and 2 MHz,
where:
BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information and Timing
AGC is selected by default, and operates by selecting the appro-
priate LNA and filter gain settings for the measured RSSI level.
It is possible to disable AGC by writing to Register 9 if you want
to enter one of the modes listed in Table 6, for example. The
time for the AGC circuit to settle and hence the time it takes to
take an accurate RSSI measurement is typically 150 μs, although
this depends on how many gain settings the AGC circuit has to
cycle through. After each gain change, the AGC loop waits for a
programmed time to allow transients to settle. This wait time
can be adjusted to speed up this settling by adjusting the
appropriate parameters.
BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)
1
IFWR
CORRECTION
A
OFFSET
IFWR
Figure 30. RSSI Block Diagram
A
R
IFWR
A
IFWR
LATCH
CLK
FSK
DEMOD
ADC
RSSI
ASK
DEMOD
Rev. 0 | Page 21 of 48
Thus, in the worst case, if the AGC loop has to go through all five
gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then
AGC settling = 10 × 5 μs × 5 = 250 μs. Minimum AGC_Wait_Time
must be at least 25 μs.
RSSI Formula (Converting to dBm)
where:
Readback_Code is given by Bits RV7 to RV1 in the readback
register (see Readback Format section).
Gain_Mode_Correction is given by the values in Table 7.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also
obtained from the readback register.
Table 7. Gain Mode Correction
LNA Gain
(LG2, LG1)
H (1, 1)
M (1, 0)
M (1, 0)
M (1, 0)
L (0, 1)
EL (0, 0)
An additional factor should be introduced to account for losses
in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020-1
The two FSK demodulators on the ADF7020-1 are
•
•
Select these using the demodulator select bits, R4_DB (4:5).
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + F
(IF − F
from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.
AGC Settling = AGC_Wait_Time × Number of Gain Changes
Input_Power [dBm] = −120 dBm + (Readback_Code +
FSK correlator/demodulator
Linear demodulator
AGC
DEV
Gain_Mode_Correction) × 0.5
). Data is recovered by comparing the output levels
_
Wait
_
Filter Gain
(FG2, FG1)
H (1, 0)
H (1, 0)
M (0, 1)
L (0, 0)
L (0, 0)
L (0, 0)
Time
=
AGC
_
DELAY
Gain Mode Correction
0
24
45
63
90
105
×
XTAL
SEQ
ADF7020-1
_
CLK
DEV
) and
_
DIVIDE