ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 14

32bit SHARC W/SIMD Capability

ADSP-21160MKBZ-80

Manufacturer Part Number
ADSP-21160MKBZ-80
Description
32bit SHARC W/SIMD Capability
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr

Specifications of ADSP-21160MKBZ-80

Interface
Host Interface, Link Port, Serial Port
Clock Rate
80MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
400-BGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
80MHz
Mips
80
Device Input Clock Speed
80MHz
Ram Size
512KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.37/3.13V
Operating Supply Voltage (max)
2.63/3.47V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
400
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21160MKBZ-80
Manufacturer:
AD
Quantity:
310
Part Number:
ADSP-21160MKBZ-80
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21160M
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ABSOLUTE MAXIMUM RATINGS
1
ESD SENSITIVITY
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage. . . . . . . . . . . . . . . . . . –0.5 V to V
Output Voltage Swing . . . . . . . . . . . –0.5 V to V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Storage Temperature Range . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . 185ºC
Applies to input pins with internal pull-ups: DR0, DR1.
Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.
Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.
Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.
Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.
internal power measurements made using typical applications are less than specified.
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION:
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160M features proprietary ESD protection
circuitry, permanent damage may occur on devices subjected to high-energy electro-
static discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.
Applies to ACK pulled up internally with 2 k
The test program used to measure I
I
I
Idle denotes ADSP-21160M state during execution of IDLE instruction.
Characterized, but not tested.
Applies to all signal pins.
Guaranteed, but not tested.
DDINHIGH
DDINLOW
is a composite average based on a range of low activity code.
is a composite average based on a range of high activity code.
DD-INPEAK
VDD
DDEXT
DDINT
) . . . . .–0.3 V to +3.0 V
represents worst case processor operation and is not sustainable under normal application conditions. Actual
) . . . .–0.3 V to +4.6 V
)
during reset or ID2–0 = 00x.
1
. . .–0.3 V to +3.0 V
DDEXT
DDEXT
+0.5 V
+0.5 V
For more information, see Power Dissipation on page 42.
For more information, see Power Dissipation on page 42.
–14–
For more information, see Power Dissipation on page 42.
For more information, see Power Dissipation on page 42.
REV. 0

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