ADSP-21262SBBCZ150 Analog Devices Inc, ADSP-21262SBBCZ150 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21262SBBCZ150
• Description: IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SBBCZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Package: 136CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer PWM_OUT Cycle Timing
The timing specification in
Timer PWM_OUT (pulse-width modulation) mode. Timer sig-
nals are routed to the DAI_P20–1 pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Table 14. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The timing specification in
Timer WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer Width Capture Timing
Parameter
Switching Characteristic
t
Parameter
Timing Requirement
t
PWMO
PWI
DAI_P20–1
DAI_P20–1
(TIMER)
(TIMER)
Timer Pulse Width Output
Timer Pulse Width
Table 14
Table 15
and
and
Figure 12
Figure 13
Figure 13. Timer Width Capture Timing
Rev. B | Page 21 of 48 | August 2005
applies to
applies to
Figure 12. Timer PWM_OUT Timing
Min
2 t
Min
2 t
CCLK
CCLK
t
PWMO
– 1
t
PWI
Max
2(2
Max
2(2
31
31
– 1) t
– 1) t
CCLK
CCLK
ADSP-21262
Unit
ns
Unit
ns