ADSP-21262SBBCZ150 Analog Devices Inc, ADSP-21262SBBCZ150 Datasheet - Page 28

IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC

ADSP-21262SBBCZ150

Manufacturer Part Number
ADSP-21262SBBCZ150
Description
IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr

Specifications of ADSP-21262SBBCZ150

Interface
DAI, SPI
Clock Rate
150MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
136-CSPBGA
Device Core Size
32/40Bit
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
150MHz
Mips
150
Device Input Clock Speed
150MHz
Ram Size
256KB
Program Memory Size
512KB
Operating Supply Voltage (typ)
1.2/3.3V
Operating Supply Voltage (min)
1.14/3.13V
Operating Supply Voltage (max)
1.26/3.47V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
136
Package Type
CSPBGA
Package
136CSP-BGA
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
150 MHz
Device Million Instructions Per Second
150 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21262SBBCZ150
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21262SBBCZ150
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21262
Table 22. 16-Bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
D = (data cycle duration) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEW
ALERW
ADAS
ADAH
WW
ALEHZ
DWS
DWH
CCLK
(if a hold cycle is specified, else H = 0)
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data15–0 Hold After ALE Deasserted
WR Pulse Width
ALE Deasserted
Address/Data15–0 Setup Before WR High
Address/Data15–0 Hold After WR High
AD15-0
ALE
WR
RD
CCLK
1
to Address/Data15–0 in High Z
VALID ADDRESS
t
ADAS
t
ALEW
Figure 20. 16-Bit Memory Write Cycle
Rev. B | Page 28 of 48 | August 2005
t
ADAH
t
ALEH
t
ALERW
1
1
t
t
DWS
VALID DATA
WW
Min
2 × t
1 × t
2.5 × t
0.5 × t
D – 2
0.5 × t
D
0.5 × t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
– 2
– 0.5
t
DWH
– 2.0
– 0.8
– 0.8
– 1.5 + H
Max
0.5t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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