ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 9
![IC,Battery Management,QFP,48PIN,PLASTIC](/photos/6/59/65923/505-48-lqfp_sml.jpg)
ADUC7032BSTZ-8L-RL
Manufacturer Part Number
ADUC7032BSTZ-8L-RL
Description
IC,Battery Management,QFP,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of ADUC7032BSTZ-8L-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Table 3. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data output setup time before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
t
DOSU
t
DSU
1
1
MSB IN
MSB
t
DHD
t
SH
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
t
DF
2
HCLK
t
DAV
2
= t
UCLK
t
SL
/2
Rev.0 | Page 9 of 116
CD
t
DR
.
BITS[6:1]
BITS[6:1]
Min
0
3 × t
UCLK
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
½ t
3.5
3.5
3.5
3.5
LSB IN
SL
t
SR
LSB
HCLK
HCLK
t
SF
Max
(2 × t
UCLK
) + (2 × t
ADuC7032-8L
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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