ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 97

IC,Battery Management,QFP,48PIN,PLASTIC

ADUC7032BSTZ-8L-RL

Manufacturer Part Number
ADUC7032BSTZ-8L-RL
Description
IC,Battery Management,QFP,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7032BSTZ-8L-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
UART Control Register 1
Name: COMCON1
Address: 0xFFFF0710
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0.
Table 82. COMCON1 MMR Bit Designations
Bit
7 to 6
5
4
3 to 0
UART Status Register 0
Name: COMSTA0
Address: 0xFFFF0714
Default Value: 0x60
Access: Read only
Function: This 8-bit read-only register reflects the current status on the UART.
Table 83. COMSTA0 MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
Name
LOOPBACK
Name
TEMT
THRE
BI
FE
PE
OE
DR
Description
UART Input Multiplexer.
Not Used. 0 by default.
Loop Back. Set by user to enable loopback mode. In loopback mode, the TxD is forced high.
Not Used. 0 by default.
Description
Reserved.
COMTX and Shift Register Empty Status Bit.
COMTX Empty Status Bit.
Break Indicator.
Parity Error.
Framing Error.
Overrun Error.
Data Ready.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted;
that is, it is no longer present in the shift register.
Cleared automatically when writing to COMTX.
Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set. The previous data may
not have been transmitted yet and may still be present in the shift register.
Cleared automatically when writing to COMTX.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
Set when the stop bit is invalid.
Cleared automatically.
Set when a parity error occurs.
Cleared automatically.
Set automatically if data is overwritten before having been read.
Cleared automatically.
Set automatically when COMRX is full.
Cleared by reading COMRX.
00 = RxD driven by LIN input; required for LIN communications via LIN pin.
01 = reserved.
10 = RxD driven by GPIO_5; required for serial communications via GPIO_5 pin (RxD).
11 = reserved.
Rev.0 | Page 97 of 116
ADuC7032-8L

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