ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 98
![IC,Battery Management,QFP,48PIN,PLASTIC](/photos/6/59/65923/505-48-lqfp_sml.jpg)
ADUC7032BSTZ-8L-RL
Manufacturer Part Number
ADUC7032BSTZ-8L-RL
Description
IC,Battery Management,QFP,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of ADUC7032BSTZ-8L-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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ADuC7032-8L
UART Interrupt Enable Register 0
Name: COMIEN0
Address: 0xFFFF0704
Default Value: 0x00
Access: Read/write
Function: This 8-bit register enables and disables the individual UART interrupt sources.
Table 84. COMIEN0 MMR Bit Designations
Bit
7 to 3
2
1
0
UART Interrupt Identification Register 0
Name: COMIID0
Address: 0xFFFF0708
Default Value: 0x01
Access: Read only
Function: This 8-bit register reflects the source of the UART interrupt.
Table 85. COMIID0 MMR Bit Designations
Bits[2:1]
Status Bits
00
11
10
01
00
UART Fractional Divider Register
Name: COMDIV2
Address: 0xFFFF072C
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register controls the operation of the ADuC7032-8L fractional divider.
Table 86. COMDIV2 MMR Bit Designations
Bit
15
14 to 13
12 to 11
10 to 0
Name
ELSI
ETBEI
ERBFI
Bit 0 NINT
1
0
0
0
0
Name
FBEN
FBM[1:0]
Description
COMRX Status Interrupt Enable Bit.
Enable Transmit Buffer Empty Interrupt.
Enable Receive Buffer Full Interrupt.
FBN[10:0]
Not Used. 0 by default.
Set by user to enable generation of an interrupt if any of COMSTA0[3:1] are set.
Cleared by user.
Set by user to enable interrupt when buffer is empty during a transmission, that is, when COMSTA[5] is set.
Cleared by user.
Set by user to enable interrupt when buffer is full during a reception.
Cleared by user.
Priority
N/A
1
2
3
4
Description
Fractional Baud Rate Generator Enable Bit.
Reserved.
M. If FBM = 0, M = 4.
N.
Set by user to enable the fractional baud rate generator.
Cleared by user to generate baud rate using the standard 450 UART baud rate generator.
Definition
No Interrupt.
Receive Line Status Interrupt.
Receive Buffer Full Interrupt.
Transmit Buffer Empty Interrupt.
Modem Status Interrupt.
Rev.0 | Page 98 of 116
Clearing Operation
N/A
Read COMSTA0.
Read COMRX.
Write data to COMTX or read COMIID0.
Read COMSTA1.
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