ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 20

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7124/ADuC7126
Pin No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
P3.3/AD3/PWM3/PLAI[11]
P2.4/SPM13/PWM0/MS0/SOUT1
P0.3/TRST/A16/ADC
P2.5/PWM1/MS1
P2.6/PWM2/MS2
P3.4/AD4/PWM4/PLAI[12]
P3.5/AD5/PWM5/PLAI[13]
RST
IRQ0/P0.4/PWM
IRQ1/P0.5/ADC
P2.7/PWM3/MS3
P2.0/SPM9/PLAO[5]/ CONV
P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0
IOGND
IOV
DD
BUSY
TRIP
/PLAO[2]/MS2
/PLAO[1]/MS1
BUSY
START
/SOUT0
Description
General-Purpose Input and Output Port 3.3 (P3.3).
External Memory Interface (AD3).
PWM Phase 3 (PWM3).
Programmable Logic Array Input Element 11 (PLAI[11]).
General-Purpose Input and Output Port 2.4 (P2.4).
Serial Port Multiplexed (SPM13)
PWM Phase 0 (PWM0).
External Memory Select 0 (MS0).
UART1 Output (SOUT1).
General-Purpose Input and Output Port 0.3 (P0.3).
JTAG Test Port Input, Test Reset (TRST).JTAG Reset Input. Debug and download access. If
this pin is held low, JTAG access is not possible because the JTAG interface is held in
reset and P0.1/P0.2/P0.3 are configured as GPIO pins.
Address Line (A16).
ADC
General-Purpose Input and Output Port 2.5 (P2.5).
PWM Phase 1 (PWM1).
External Memory Select 1 (MS1).
General-Purpose Input and Output Port 2.6 (P2.6).
PWM Phase 2 (PWM2).
External Memory Select 2 (MS2).
General-Purpose Input and Output Port 3.4 (P3.4).
External Memory Interface (AD4).
PWM Phase 4 (PWM4).
Programmable Logic Array Input 12 (PLAI[12]).
General-Purpose Input and Output Port 3.5 (P3.5).
External Memory Interface (AD5).
PWM Phase 5 (PWM5).
Programmable Logic Array Input Element 13 (PLAI[13]).
Reset Input, Active Low.
Multifunction I/O Pin.
External Interrupt Request 0, Active High (IRQ0).
General-Purpose Input and Output Port 0.4 (P0.4).
PWM Trip External Input (PWM
Programmable Logic Array Output Element 1 (PLAO[1]).
External Memory Select 1 (MS1)..
Multifunction I/O Pin.
External Interrupt Request 1, Active High (IRQ1).
General-Purpose Input and Output Port 0.5 (P0.5).
ADC
Programmable Logic Array Output Element 2 (PLAO[2]).
External Memory Select 2 (MS2).
General-Purpose Input and Output Port 2.7 (P2.7).
PWM Phase 3 (PWM3).
External Memory Select 3 (MS3).
General-Purpose Input and Output Port 2.0 (P2.0).
Serial Port Multiplexed (SPM9).
Programmable Logic Array Output Element 5 (PLAO[5]).
Start Conversion Input Signal for ADC (
UART0 Output (SOUT0).
General-Purpose Input and Output Port 0.7 (P0.7).
Serial Port Multiplexed (SPM8).
Output for External Clock Signal (ECLK).
Input to the Internal Clock Generator Circuits (XCLK).
Programmable Logic Array Output Element 4 (PLAO[4]).
UART0 Input (SIN0).
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
BUSY
BUSY
Signal Output (ADC
Signal Output (ADC
Rev. B | Page 20 of 104
BUSY
BUSY
).
TRIP
).
).
CONV
START
).