ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 47
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ADUC7124BCPZ126-RL
Manufacturer Part Number
ADUC7124BCPZ126-RL
Description
ARM7 With 12-Bit ADC & DACs, 128kB Flash
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7126BSTZ126.pdf
(104 pages)
Specifications of ADUC7124BCPZ126-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
41.78MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
30
Program Memory Size
126KB (63K x 16)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7124BCPZ126-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Table 54. FEExMOD MMR Bit Descriptions
Bit
[7:5]
4
3
2
[1:0]
Table 55. Command Codes in FEExCON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
The FEExCON register always reads 0x07 immediately after execution of any of these commands.
1
1
1
1
1
1
1
Command
Null
Single read
Single write
Erase/write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Reserved
Reserved
Ping
Description
Reserved.
Flash/EE interrupt enable.
Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
Cleared by the user to disable the Flash/EE interrupt.
Erase/write command protection.
Set by the user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against the erase/write command.
Reserved. Should always be set to 0 by the user.
Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect.
Description
Idle state.
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 µs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed to by FEExADR. This operation
takes 20 ms.
Compare the contents of the location pointed to by FEExADR to the data in FEExDAT. The result of the
comparison is returned in FEExSTA, Bit 1.
Erase the page indexed by FEExADR.
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
Reserved.
Reserved.
Reserved.
Reserved.
Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the key.
Reserved.
Reserved.
No operation, interrupt generated.
Rev. B | Page 47 of 104
ADuC7124/ADuC7126