CS2000CP-DZZ Cirrus Logic Inc, CS2000CP-DZZ Datasheet - Page 19

• Manufacturer Part Number: CS2000CP-DZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS761PP1
5.3.5
set to 10), the Frequency Range Indicator would then reflect the frequency range of the audio sample rate.
An R
Effective Ratio (R
The Effective Ratio (R
previously described. R
Frequency Synthesizer (Static Ratio) Mode: R
Hybrid PLL (Dynamic Ratio) Mode: R
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of R
if R
12.20 format. In all cases, the maximum and minimum allowable values for R
quency limits for both the input and output clocks as shown in the
page
Selection of the user defined ratio from the four stored ratios is made by using the RSel[1:0] bits unless
auto clock switching is enabled in which case the LockClk[1:0] bits also select the ratio (see
tional-N Source Selection for the Frequency Synthesizer” on page
Referenced Control
Ratio 0-3
RModSel[2:0]
AutoRMod
Referenced Control
RSel[1:0]
LockClk[1:0]
FsDetect[1:0]
UD
UD
8.
is 1024 an R
.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
of 512 would then generate the audio oversampling clocks as shown in
...............................“Ratio Selection (RSel[1:0])” on page 28
00
01
10
.............................“Auto R-Modifier Enable (AutoRMod)” on page 29
..........................“Lock Clock Ratio (LockClk[1:0])” section on page 29
........................“R-Mod Selection (RModSel[2:0])” section on page 28
Table 4. Example Audio Oversampling Clock Generation from CLK_IN
MOD
Inferred Audio Sample Rate
when SysClk=12.288 MHz
EFF
EFF
Register Location
Register Location
EFF
of 8 would produce an R
) is an internal calculation comprised of R
54.8 kHz to 128 kHz
)
is calculated as follows:
< 54.8 kHz
> 128 kHz
EFF
= R
UD
EFF
•
EFF
R
= R
MOD
Speed Mode (used for
UD
value of 8192 which exceeds the 4096 limit of the
audio converters)
•
•
Auto R-Mod
Double Speed
R
Single Speed
Quad Speed
MOD
20).
EFF
UD
“AC Electrical Characteristics” on
and the appropriate modifiers, as
should not be used; For example
EFF
Table
Audio Oversampling
are dictated by the fre-
4.
CS2000-CP
Clock
512 x
256 x
128 x
“Manual Frac-
19