CS2000CP-DZZ Cirrus Logic Inc, CS2000CP-DZZ Datasheet - Page 29

• Manufacturer Part Number: CS2000CP-DZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS761PP1
8.3.3
8.3.4
8.4
8.4.1
8.4.2
Reserved
7
Device Configuration 2 (Address 04h)
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
Note:
tion (AuxLockCfg)” on page
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, enables control port mode. Both bits must be set to 1 during ini-
tialization.
Note:
Auto R-Modifier Enable (AutoRMod)
Controls the automatic ratio modifier function.
Lock Clock Ratio (LockClk[1:0])
Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.
AuxOutSrc[1:0]
00
01
10
11
Application:
EnDevCfg1
0
1
Application:
AutoRMod
0
1
Application:
LockClk[1:0]
00
01
10
11
Application:
Reserved
When set to 11, AuxLckCfg sets the polarity and driver type
EnDevCfg2 must also be set to enable control port mode
6
Auxiliary Output Source
RefClk.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 22
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
Automatic R-Mod State
Disabled.
Enabled.
“Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only” on page 18
CLK_IN Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
Section 5.3.2 on page 17
Reserved
5
31).
Reserved
4
AutoRMod
3
LockClk1
(“SPI / I²C Control Port” on page
2
(“AUX PLL Lock Output Configura-
LockClk0
1
CS2000-CP
FracNSrc
0
24).
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