CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 17

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS470F4
5.8
VLRCK
Output
RCBL
C, U
Out
Mono Mode Operation
An AES3 stream may be used in more than one way to transmit 96 kHz sample rate data. One method is
to double the frame rate of the current format. This results in a stereo signal with a sample rate of 96 kHz,
carried over a single twisted pair cable. An alternate method is implemented using the 2 sub-frames in a 48-
kHz frame rate AES3 signal to carry consecutive samples of a mono signal, resulting in a 96-kHz sample
rate stream. This allows older equipment, whose AES3 transmitters and receivers are not rated for 96-kHz
frame rate operation, to handle 96-kHz sample rate information. In this “mono mode”, 2 AES3 cables are
needed for stereo data transfer. The CS8415A offers mono mode operation, controlled through the MMR
control register bit.
The receiver mono mode effectively doubles Fs compared to the input frame rate. The clock output on the
RMCK pin tracks Fs, and so is doubled in frequency compared to stereo mode. The receiver will run at a
frame rate of Fs/2, and the serial audio output port will run at Fs. Sub-frame A data will be routed to both
the left and right data fields on SDOUT. Similarly, sub-frame B data will be routed to both the left and right
data fields of the next word clock cycle of SDOUT.
Using mono mode is only necessary if the serial audio output port must run at 96 kHz. If the CS8415A is
kept in normal stereo mode, and receives AES3 data arranged in mono mode, then the serial audio output
port will run at 48 kHz, with left and right data fields representing consecutive audio samples.
- RCBL and C output are only available in hardware mode.
- RCBL goes high 2 frames after receipt of a Z preamble, and is high for 16 frames.
- VLRCK is a virtual word clock, which may not exist, but is used to illustrate the C/U timing.
- VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
- If the serial audio output port is in master mode, VLRCK = OLRCK
- If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
- C and U transitions are aligned within ± 1% of VLRCK period to VLRCK edges.
Figure 7. AES3 ReceiverTiming for C & U Pin Output Data
CS8415A
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