CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 21

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS470F4
8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
8.2
SWCLK
7
7
0
Control 1 (01h)
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
Default = ‘0’
0 - RMCK default function
1 - OMCK output on RMCK pin
MUTESAO - Mute control for the serial audio output port
Default = ‘0’
0 - Disabled
1 - Enabled
INT1:0 - Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Control 2 (02h)
HOLD1:0 - Determine how received audio sample is affected when a receiver error occurs
Default = ‘00’
00 - Hold the last valid audio sample
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
RMCKF - Select recovered master clock output pin frequency.
Default = ‘0’
0 - RMCK is equal to 256 * Fs
1 - RMCK is equal to 128 * Fs
MMR - Select AES3 receiver mono or stereo operation
Default = ‘0’
0 - Normal stereo operation
1 - A and B subframes treated as consecutive samples of one channel of data.
Data is duplicated to both left and right parallel outputs of the AES receiver block.
The sample rate (Fs) is doubled compared to MMR=0
HOLD1
6
6
0
MUTESAO
HOLD0
5
5
RMCKF
4
4
0
MMR
3
0
3
MUX2
INT1
2
2
MUX1
INT0
1
1
CS8415A
MUX0
0
0
0
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