CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 32

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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10.HARDWARE MODE
The CS8415A has a hardware mode which allows using the device without a microcontroller. Hardware mode is
selected by connecting the H/S pin to VL+. Various pins change function in hardware mode, described in the hard-
ware mode pin definition section.
Hardware mode data flow is shown in
serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The
decoded C and U bits are also output, clocked at both edges of OLRCK (master mode only, see Figure 7).The cur-
rent audio sample is passed unmodified to the serial audio output port if the validity bit is high, or a parity, bi-phase,
or PLL lock error occurs.
10.1
OF1 - Left Justified
OF2 - I²S 24-bit data
OF3 - Right Justified, master mode only
OF4 - Direct AES3 data
Serial Audio Port Formats
In hardware mode, only a limited number of alternative serial audio port formats are available.
fines the equivalent software mode bit settings for each format. Start-up options are shown in
allow choice of the serial audio output port as a master or slave, and the serial audio port format.
SDOUT
RXP
RXN
LO
HI
-
-
-
-
RM CK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Table 2. Equivalent Software Mode Bit Definitions
AES3 Rx
&
Decoder
RERR
Table 3. Hardware Mode Start-Up Options
ORIG
Figure
LO
LO
HI
HI
-
-
NVERR
Figure 10. Hardware Mode
10. Audio data is input through the AES3 receiver, and routed to the
EMPH
CHS
SOSF SORES1/0 SOJUST
LO
LO
HI
HI
-
-
0
0
0
0
COPY ORIG
C & U bit Data Buffer
V L +
H/S
Serial Output Port is Master
00
00
00
11
Serial Output Port is Slave
EM PH
Direct AES3 data
PRO AUDIO
I²S 24-bit data
Right Justified
Left Justified
Function
0
0
1
0
Serial
Audio
Output
RCBL
SODEL SOSPOL SOLRPOL
0
1
0
0
OLRCK
OSCLK
SDOUT
C
U
0
0
0
0
CS8415A
Table
Table 2
DS470F4
0
1
0
0
3, and
de-