CY7C009V-15AXC Cypress Semiconductor Corp, CY7C009V-15AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C009V-15AXC
• Description: CY7C009V-15AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C009V-15AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1M (128K x 8)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1786

Switching Waveforms
Document Number: 38-06044 Rev. *E
Write Cycle No. 1: R/W Controlled Timing
Write Cycle No. 2: CE Controlled Timing
Notes
CE
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
[32]
HA
[32]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
.
t
t
SA
SA
NOTE 34
(continued)
SCE
IH
.
or t
SD
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM.
t
HZWE
[28, 29, 30, 35]
[33]
[28, 29, 30, 31]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
CY7C008V/009V
CY7C018V/019V
[33]
NOTE 34
Page 12 of 23
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