CY7C1412AV18-200BZXC Cypress Semiconductor Corp, CY7C1412AV18-200BZXC Datasheet - Page 17
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CY7C1412AV18-200BZXC
Manufacturer Part Number
CY7C1412AV18-200BZXC
Description
CY7C1412AV18-200BZXC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1412AV18-200BZXC.pdf
(27 pages)
Specifications of CY7C1412AV18-200BZXC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
36M (2M x 18)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2160
CY7C1412AV18-200BZXC
CY7C1412AV18-200BZXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1412AV18-200BZXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■
■
Document #: 38-05615 Rev. *H
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐
❐
❐
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
Apply V
Apply V
Drive DOFF HIGH.
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
.
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
Figure 3. Power Up Waveforms
/
V
REF
DDQ
.
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Fix High (or tie to V DDQ )
> 1024 Stable clock
Stable)
CY7C1412AV18
CY7C1414AV18
Start Normal
Operation
KC Var
Page 17 of 27
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