CY7C1412AV18-200BZXC Cypress Semiconductor Corp, CY7C1412AV18-200BZXC Datasheet - Page 8
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CY7C1412AV18-200BZXC
Manufacturer Part Number
CY7C1412AV18-200BZXC
Description
CY7C1412AV18-200BZXC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1412AV18-200BZXC.pdf
(27 pages)
Specifications of CY7C1412AV18-200BZXC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
36M (2M x 18)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2160
CY7C1412AV18-200BZXC
CY7C1412AV18-200BZXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1412AV18-200BZXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Truth Table
The truth table for CY7C1412AV18, and CY7C1414AV18 follows.
Write Cycle Descriptions
The write cycle description table for CY7C1412AV18 follows.
Notes
Document #: 38-05615 Rev. *H
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
BWS
H
H
H
H
symmetrically.
of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
0
BWS
H
H
H
H
L
L
L
L
1
L–H
L–H
L–H
L–H
K
–
–
–
–
Operation
L–H During the data portion of a write sequence
L–H During the data portion of a write sequence
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence
K
–
–
–
–
During the data portion of a write sequence
Both bytes (D
Both bytes (D
During the data portion of a write sequence
Only the lower byte (D
Only the lower byte (D
During the data portion of a write sequence
Only the upper byte (D
Only the upper byte (D
No data is written into the devices during this portion of a write operation.
represents rising edge.
[17:0]
[17:0]
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
Write Cycle Descriptions
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
[2, 8]
Stopped
L-H
L-H
L-H
[2, 3, 4, 5, 6, 7]
K
RPS WPS
table. BWS
H
X
L
X
Comments
H
L
X
X
0
, BWS
[17:9]
[17:9]
D(A + 0) at K(t)
Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
D = X
Q = High Z
Previous State
[8:0]
[8:0]
1,
BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
2
and BWS
DQ
3
can be altered on different portions
CY7C1412AV18
CY7C1414AV18
D(A + 1) at K(t)
D = X
Q = High Z
Previous State
DQ
Page 8 of 27
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