CY7C1460AV25-200BZXC Cypress Semiconductor Corp, CY7C1460AV25-200BZXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1460AV25-200BZXC
• Description: CY7C1460AV25-200BZXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
package). When this scan cell, called the “extest output bus
tri-state,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place the
output bus into a high Z condition.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05354 Rev. *G
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
12. t
13. Test conditions are specified using the load in TAP AC test Conditions. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Mode Select
[12, 13]
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
Description
1
t TMSS
t TDIS
2
t TMSH
t TDIH
R
t TH
/t
F
DON’T CARE
= 1 ns.
t
TL
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
t CYC
UNDEFINED
4
t TDOX
t TDOV
Min
5
50
20
20
–
–
0
5
5
5
5
5
5
6
Max
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
20
10
–
–
–
–
–
–
–
–
–
–
Page 14 of 29
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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