CY7C1480BV25-200BZC Cypress Semiconductor Corp, CY7C1480BV25-200BZC Datasheet - Page 13

• Manufacturer Part Number: CY7C1480BV25-200BZC
• Description: CY7C1480BV25-200BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incor-
porates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V I/O logic levels.
The
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to V
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Figure 2. TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document Number: 001-15143 Rev. *F
DD
1
0
through a pull up resistor. TDO must be left unconnected.
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
EXIT1-DR
EXIT2-DR
DR-SCA N
SHIFT-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
SS
1
1
0
0
) to
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the
TDI is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant
bit (MSB) of any register. (See
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit (LSB)
of any register. (See
Figure 3. TAP Controller Block Diagram
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
TM S
TCK
TDI
CY7C1482BV25, CY7C1486BV25
Selection
Circuitry
TAP Controller State
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
30
.
29
Bypass Register
.
.
.
TAP Controller Block
.
.
TAP Controller State
.
.
2
2
2
CY7C1480BV25
1
1
1
0
0
0
0
Diagram.)
Selection
DD
Circuitry
) for five rising
Page 13 of 31
Diagram.)
Diagram.
TDO
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