CY7C1480V33-250BZI Cypress Semiconductor Corp, CY7C1480V33-250BZI Datasheet
CY7C1480V33-250BZI
Specifications of CY7C1480V33-250BZI
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CY7C1480V33-250BZI Summary of contents
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... Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • CY7C1480V33, CY7C1482V33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1486V33 available in lead-free and non-lead-free 209 ball FBGA package • ...
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... Logic Block Diagram – CY7C1480V33 (2M x 36) A0, A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP DQ DQP BYTE BW D WRITE REGISTER DQ DQP BYTE BW C WRITE REGISTER DQ DQP BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL 2 Logic Block Diagram – ...
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... WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480V33 CY7C1482V33 CY7C1486V33 OUTPUT OUTPUT SENSE DQs BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP ...
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... TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ CY7C1482V33 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ SSQ DDQ 27 DDQ DQP CY7C1480V33 CY7C1482V33 CY7C1486V33 DDQ V 76 SSQ NC 75 DQP SSQ 70 V DDQ ( DDQ 60 V SSQ SSQ V 54 DDQ Page [+] Feedback ...
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... DDQ DDQ DDQ DDQ N DQP DDQ MODE NC/288M NC/144M CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document #: 38-05283 Rev. *G 165-ball FBGA ( 1.4 mm) Pinout CY7C1480V33 ( BWE CLK TDI A1 TDO TCK TMS CY7C1482V33 ( BWE B ...
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... ADSC ADSP ADV 2 A NC/288M BWE BWS C G NC/144M NC/576M BWS NC/ DDQ DDQ DDQ DDQ DDQ DDQ MODE TDI CY7C1480V33 CY7C1482V33 CY7C1486V33 BWS DQ BWS BWS DQ DQ BWS DQP DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQ DDQ DQP DQP ...
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... The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP condition. Ground for the core of the device. Ground for the I/O circuitry. Power supply for the I/O circuitry. CY7C1480V33 CY7C1482V33 CY7C1486V33 , CE , and CE are sampled ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... ADSC CY7C1480V33 CY7C1482V33 CY7C1486V33 ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State L L-H Tri-State L-H Tri-State L L-H Tri-State L L Writes may occur only on subsequent clocks X Page [+] Feedback ...
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... Truth Table for Read/Write Function (CY7C1480V33) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – (DQ and DQP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480V33/CY7C1482V33/CY7C1486V33 incorpo- rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a portion of SAMPLE/PRELOAD instruction. If this is an issue still CY7C1480V33 CY7C1482V33 CY7C1486V33 Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [8, 9] Over the Operating Range Description / ns CY7C1480V33 CY7C1482V33 CY7C1486V33 TDOV Min. Max. Unit MHz ...
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... GND < V < DDQ CY7C1482V33 CY7C1486V33 (4M x 18) (1M x72) 000 000 000 01011 01011 01011 000000 000000 010100 110100 00000110100 00000110100 Allows unique identification of SRAM CY7C1480V33 CY7C1482V33 CY7C1486V33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0 ...
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... N6 46 H11 P11 47 G11 R8 48 F11 P3 49 E11 P4 50 D10 P8 51 D11 P9 52 C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit Size (x72 112 Bit # 165-Ball Page [+] Feedback ...
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... Boundary Scan Exit Order (4M x 18) Bit # 165-Ball P11 Document #: 38-05283 Rev. *G Bit # 165-Ball P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit # 165-Ball ID 37 C11 38 A11 39 A10 40 B10 Page [+] Feedback ...
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... W6 71 L10 J11 V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit # 209-Ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 100 A8 101 B4 102 B3 103 ...
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... Max, Device Deselected, All speeds DD ≥ V ≤ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480V33 CY7C1482V33 CY7C1486V33 + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V –5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3.135 ...
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... EIA/JESD51 317Ω 3.3V V OUTPUT DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1480V33 CY7C1482V33 CY7C1486V33 165 FBGA 209 FBGA Max. Max. Unit ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1480V33 CY7C1482V33 CY7C1486V33 200 MHz 167 MHz Min. Max. Min. Max. Unit ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1480V33 CY7C1482V33 CY7C1486V33 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05283 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1480V33 CY7C1482V33 CY7C1486V33 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3) ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24 HIGH. Document #: 38-05283 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1480V33 CY7C1482V33 CY7C1486V33 A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05283 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1480V33 CY7C1482V33 CY7C1486V33 Page [+] Feedback ...
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... CY7C1480V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1482V33-167AXC CY7C1480V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) CY7C1482V33-167BZC CY7C1480V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) Lead-Free CY7C1482V33-167BZXC CY7C1486V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1486V33-167BGXC CY7C1480V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack ( ...
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... CY7C1486V33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1486V33-250BGXC CY7C1480V33-250AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1482V33-250AXI CY7C1480V33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) CY7C1482V33-250BZI CY7C1480V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) Lead-Free CY7C1482V33-250BZXI CY7C1486V33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1480V33 CY7C1482V33 CY7C1486V33 1.40±0.05 12°±1° A ...
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... Package Diagrams (continued) 165-ball FBGA ( 1.4 mm) (51-85165) TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 38-05283 Rev 0.15(4X) CY7C1480V33 CY7C1482V33 CY7C1486V33 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 15.00±0.10 51-85165-*A Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1480V33 CY7C1482V33 ...
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... History Page Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 38-05283 REV. ECN NO. Issue Date ** 114670 08/06/02 *A 118281 01/21/03 *B 233368 See ECN *C 299452 See ECN *D 323080 See ECN *E 416193 See ECN *F 470723 See ECN *G 486690 See ECN Document #: 38-05283 Rev ...