CY7C1480V33-167AXC Cypress Semiconductor Corp, CY7C1480V33-167AXC Datasheet
CY7C1480V33-167AXC
Specifications of CY7C1480V33-167AXC
CY7C1480V33-167AXC
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CY7C1480V33-167AXC Summary of contents
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... Separate processor and controller address strobes • Synchronous self timed writes • Asynchronous output enable • Single cycle chip deselect • CY7C1480V33, CY7C1482V33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1486V33 available in Pb-free and non-Pb-free 209-ball FBGA package • ...
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... Logic Block Diagram – CY7C1480V33 ( A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C WRITE REGISTER BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1482V33 (4M x 18) ...
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... WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480V33 CY7C1482V33 CY7C1486V33 OUTPUT OUTPUT SENSE DQs BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP ...
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... TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ CY7C1482V33 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ DDQ DQP CY7C1480V33 CY7C1482V33 CY7C1486V33 DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ ( DDQ 60 V SSQ SSQ V 54 DDQ Page [+] Feedback ...
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... C C DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE NC/288M NC/144M A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document Number: 38-05283 Rev. *J CY7C1480V33 ( BWE CLK TDI A1 TDO TCK TMS CY7C1482V33 ( BWE CLK ...
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... CE ADSC ADSP ADV 2 A NC/288M BWE BWS C G NC/144M NC/576M BWS NC/ DDQ DDQ DDQ DDQ DDQ DDQ MODE TDI CY7C1480V33 CY7C1482V33 CY7C1486V33 BWS DQ BWS BWS DQ BWS DQP DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQ DDQ DQP DQP DDQ ...
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... LOW, the pins behave as outputs. When HIGH, DQs and DQP in a tri-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the I/O circuitry. serves as ground for the core and the IO circuitry. SS CY7C1480V33 CY7C1482V33 CY7C1486V33 , CE , and CE are 1 ...
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... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be 1 deasserted HIGH before presenting data to the DQs inputs. ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... Truth Table The Truth Table for CY7C1480V33, CY7C1482V33, and CY7C1486V33 follows. Operation Add. Used Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Sleep Mode, Power Down ...
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... Truth Table for Read/Write The following is a Truth Table for Read/Write for the CY7C1480V33. Function Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480V33/CY7C1482V33/CY7C1486V33 incorpo- rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus portion of CY7C1480V33 CY7C1482V33 CY7C1486V33 Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOX DON’ UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1480V33 CY7C1482V33 CY7C1486V33 TDOV Min. Max. Unit MHz ...
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... GND < V < DDQ CY7C1482V33 CY7C1486V33 (4M x 18) (1M x72) 000 000 000 01011 01011 01011 000000 000000 010100 110100 00000110100 00000110100 Enables unique identification of SRAM CY7C1480V33 CY7C1482V33 CY7C1486V33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0 ...
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... N6 46 H11 P11 47 G11 R8 48 F11 P3 49 E11 P4 50 D10 P8 51 D11 P9 52 C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit Size (x72 112 Bit # 165-Ball Page [+] Feedback ...
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... Boundary Scan Exit Order (4M x 18) Bit # 165-Ball P11 Document Number: 38-05283 Rev. *J Bit # 165-Ball P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit # 165-Ball ID 37 C11 38 A11 39 A10 40 B10 Page [+] Feedback ...
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... W6 71 L10 J11 V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480V33 CY7C1482V33 CY7C1486V33 Bit # 209-Ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 100 A8 101 B4 102 B3 103 ...
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... Max, Device Deselected, All speeds DD ≥ V ≤ /2). Undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480V33 CY7C1482V33 CY7C1486V33 + 0.5V DD Ambient DDQ Temperature 0°C to +70°C 3.3V –5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3.135 ...
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... EIA/JESD51 317Ω 3.3V V OUTPUT DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1480V33 CY7C1482V33 CY7C1486V33 165 FBGA 209 FBGA Unit Max. Max ...
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... Test Loads and Waveforms” on page is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ unless otherwise noted. CY7C1480V33 CY7C1482V33 CY7C1486V33 200 MHz 167 MHz Unit Min. Max. Min. Max. 1 ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1480V33 CY7C1482V33 CY7C1486V33 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW, and BW Document Number: 38-05283 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1480V33 CY7C1482V33 CY7C1486V33 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3) ...
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... The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 24 HIGH. Document Number: 38-05283 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1480V33 CY7C1482V33 CY7C1486V33 A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See 26. DQs are in high-Z when exiting ZZ sleep mode. Document Number: 38-05283 Rev RZZI DESELECT or READ Only High-Z DON’T CARE “Truth Table” on page 10 for all possible signal conditions to deselect the device. CY7C1480V33 CY7C1482V33 CY7C1486V33 t ZZREC Page [+] Feedback ...
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... Ordering Information Table 1. Key Features and Ordering Information Speed Package (MHz) Ordering Code Diagram 167 CY7C1480V33-167AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free 200 CY7C1480V33-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free Ordering Code Definitions V33 Document Number: 38-05283 Rev. *J Part and Package Type Voltage: 3 ...
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... Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm), 51-85050 Document Number: 38-05283 Rev. *J CY7C1480V33 CY7C1482V33 CY7C1486V33 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Figure 2. 165-Ball FBGA ( 1.4 mm), 51-85165 Document Number: 38-05283 Rev. *J CY7C1480V33 CY7C1482V33 CY7C1486V33 51-85165 *B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 3. 209-Ball FBGA ( 1.76 mm), 51-85167 Document Number: 38-05283 Rev. *J CY7C1480V33 CY7C1482V33 CY7C1486V33 51-85167 *A Page [+] Feedback ...
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... Document History Page Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 38-05283 Submission REV. ECN NO. Date ** 114670 08/06/02 *A 118281 01/21/03 *B 233368 See ECN *C 299452 See ECN *D 323080 See ECN *E 416193 See ECN *F 470723 See ECN Document Number: 38-05283 Rev. *J Orig ...
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... Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 38-05283 Submission REV. ECN NO. Date *G 486690 See ECN *H 1026720 See ECN *I 2898501 03/24/2010 *J 3067398 10/20/10 i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders Document Number: 38-05283 Rev ...