CY7C1480V33-167AXC Cypress Semiconductor Corp, CY7C1480V33-167AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C1480V33-167AXC
• Description: CY7C1480V33-167AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480V33-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2169; CY7C1480V33-167AXC

Document Number: 38-05283 Rev. *J
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480V33/CY7C1482V33/CY7C1486V33 incorpo-
rates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to V
unconnected. At power up, the device comes up in a reset
state, which will not interfere with the operation of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
1
0
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
DD
1
through a pull up resistor. TDO must be left
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCA N
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
SS
1
1
0
0
) to
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and
can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction
that is loaded into the TAP instruction register. For information
about loading the instruction register, see the
State
nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSB) of any register. (See
Controller Block
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the
TAP state machine. The output changes on the falling edge of
TCK. TDO is connected to the least significant bit (LSB) of any
register. (See
TAP Controller Block Diagram
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
TM S
TCK
TDI
Diagram. TDI is internally pulled up and can be uncon-
Selection
Circuitry
TAP Controller State
Diagram.)
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
30
.
Bypass Register
29
.
.
.
.
.
.
.
2
2
2
Diagram.)
1
1
1
CY7C1480V33
CY7C1482V33
CY7C1486V33
0
0
0
0
DD
Selection
Circuitry
TAP Controller
) for five rising
Page 12 of 31
TDO
TAP
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